On-Chip Integration of Orthogonal Subsystems Enabled by Broadband Twist at 220–325 GHz

In this article, we report for the first time on a low-loss compact platform that enables the integration of H- and E-plane rectangular waveguide subsystems enabled by 90° polarization rotation of rectangular waveguide sections on a silicon-micromachined chip. The proposed platform offers unprecedented design flexibility for a 2.5D fabrication technology such as silicon micromachining, since orthogonal waveguide device sections with full design freedom in H-plane geometries can be cofabricated with sections with full design freedom in E-plane geometries, enabled by novel, integrated waveguide twists optimized for 2.5D fabrication. The platform is developed for use in broadband millimeter- and submillimeter-wave waveguide circuits and prototypes are implemented in the 220–325-GHz band. A prototype chip demonstrating the platform, implemented by bonding three stacked silicon chips, is fabricated. The measured results of the twist prototype exhibit a very low insertion loss of less than 0.2 dB and a return loss of 20 dB or better in most of the 220–325-GHz band. An integrated eighth-degree lowpass waveguide filter with axial ports having a cut-off frequency of 280 GHz is codesigned with the twist transition and fabricated on the platform to demonstrate its application. The filter shows 0.4-dB measured insertion loss and has a measured return loss in the passband of better than 14 dB.

volume-manufacturable THz devices and systems. Future THz manufacturing methods must support the cofabrication of THz systems with different orientations enabling the interconnection of subsystems on a single platform.
The highly advanced and robust deep-silicon micromachining processes, based on proven high-volume semiconductor manufacturing methods, enable the fabrication of micrometersize features with a high-aspect ratio ideal for subterahertz and THz applications. It also enables low insertion loss due to the nanoscale roughness [6], [7], [8], [9].
Air-filled rectangular waveguides are the primary choice for THz circuits since they allow for low-loss signal routing [6]. The integration of silicon micromachined components and devices with conventional waveguide systems, and their characterization is still challenging. Traditional approaches, such as inserting the silicon chip into a CNC-milled test fixture [10], [11], [12] or using coplanar waveguide probes [13], [14], [15], [16], have numerous disadvantages, especially at sub-THz and THz frequencies, including sensitivity to misalignment, complex and expensive fabrication, radiation losses due to gaps between connectors, and parasitic coupling between probes. A silicon micromachined platform with axial waveguide interface, introduced in [17] to address these problems, enabled direct interconnection and characterization of H-plane waveguide circuits (here, H-plane waveguides refers to having the H-plane in-plane with the wafer surface, i.e., orthogonal to the direction of etching) integrated on a single chip, including narrowband bandpass filters with unparalleled fabrication accuracy. For bandpass filters, all the geometries defining their performance, such as cavity and inductive-coupling irises sizes, have the same waveguide heights and thus require a single etching step for their fabrication. However, for lowpass filters (LPFs) traditionally designed using cascaded sections of capacitive irises, their integration in a silicon micromachined H-plane waveguide circuit would require as many different etching steps as there are waveguide sections of various heights in a design, which makes the fabrication extremely complex. Alternatively, the required waveguide sections with various heights can be implemented using a single photomask if the waveguides are rotated by 90 • , so their E-plane is normal to the direction of etching. However, the transition between the H-and E-plane waveguide subsystems requires a 90 • polarization twist which is also designed for a 2.   . 1) platform. Important properties of such a twist are wideband operation, low losses, and manufacturability.
THz frequencies demand precise manufacturing with tight tolerances. The CNC milling technique is still the standard fabrication technique. Recently, a considerable amount of THz CNC-milled waveguide twists has been reported. CNC-milled single-step twists are less bulky than continuous rotation implementations; however, tight tolerances are required [20], [21], [22]. Zeng et al. [25] introduce a CNC-milled twist transition with a return loss of 25 dB. The proposed transition at 220-325 GHz has a length of 1.469 mm and has been implemented using the multistep method. Chattopadhyay et al. [26] present a twist design for the same frequency band, which has also been implemented by CNC milling and has a geometry that would also be compatible with silicon micromachining. The twist is performed in several steps and is quite large, with a total length of 6 mm, which makes it unsuitable for compact on-chip systems.
This article presents a novel on-chip integrated full-band silicon micromachined rectangular waveguide 90 • twist operating at subterahertz frequencies. The proposed twist provides on-chip interconnection of H-and E-plane waveguide subsystems in the same platform and allows larger device design freedom for the 2.5D fabrication techniques, including micromachining and computer numerical control (CNC) milling. The coexisting orthogonal waveguide subsystems combined on the same chip enable devices with complex geometries in E-plane and H-plane at a high level of integration, including the example of compact waveguide LPFs with axial chip-toflange interfaces at sub-THz frequencies, as demonstrated in this article.

II. DESIGN AND TOLERANCE ANALYSIS
A. T E 10 -to-T E 01 Transition Design Fig. 1(a) shows the proposed 90 • twist, also referred to as a TE 10 -to-TE 01 transition, integrated on a multilayer Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply. silicon-micromachined platform. The transition is designed by incrementally twisting the H-plane waveguide at the input by 90 • to obtain an orthogonal orientation of the waveguide (E-plane waveguide) at the output, and the concept was adopted to be manufacturable by micromachining, taking into account fabrication imperfections such as the effect of underetching [29], while keeping the manufacturing complexity reasonable. The transition between the input and the output is created through a waveguide taper in the middle layer connecting the input and output directly, and by two extensions in the top and the bottom layer connecting to the E-plane waveguide, bent in opposed directions and shorted at the H-plane waveguide's input. The detailed geometrical dimensions of the implemented waveguide transition are shown in Fig. 1. To facilitate the fabrication, the structure uses only three gold-metalized silicon layers, which have been chosen as a tradeoff between the simplicity of manufacturing and the electrical performance of the transition. This three-layer structure consists of an input H-plane waveguide, supporting propagation of the TE 10 mode in the middle layer, and an output E-plane waveguide that confines the TE 01 mode in three layers.
The transition was optimized using a full-wave 3-D finiteelement electromagnetic solver (CST microwave studio) for its four design parameters [s1, s2, L E, and L T ; see Fig. 1(d)] to achieve more than 20 dB return loss throughout the entire 220-325-GHz frequency band. Fig. 2 illustrates the distribution of the electric and magnetic fields inside the transition at various cross sections. The TE 10 mode of the H-plane port twists along the transition and converts to the TE 01 mode at the E-plane port and vice versa.
The E-plane waveguide port's width and height, and the H-plane waveguide's width are defined by the WM-864 standard (864 × 432 µm), while the H-plane waveguide's height is determined by the wafer thickness (308 µm). This decreased height does not have a major impact on the performance and design implication except for slightly increased losses. The E-plane waveguide port's width is determined by the triplestack wafer thickness (864 µm). Utilization of a single wafer for manufacturing, the ability to achieve the standard width for the E-plane waveguide, and keeping the fabrication simple determined the H-plane waveguide's height. The dimensions are shown in Table I.

B. Performance and Tolerance Analysis
Underetching is a common fabrication phenomenon in deep reactive ion etching (DRIE) of large cavities, which, if left uncompensated, impacts the device's performance [8], [29]. Fig. 3 shows the return loss of the transition, including the influence of the nonverticality of sidewalls on the performance, for 0-, 10-, and 20-µm underetching. The underetching is avoided in the middle layer since it is manufactured using fall-out structures, resulting in close-to-zero underetching [23], but the extensional features located in the top and the bottom layers are inevitably affected by underetching, due to their large etching area.
Another performance-influencing factor is the misalignment of the stacked layers. Fig. 4 shows the influence of this effect on the return loss, with 20 random sample points for the misalignment between adjacent chip layers in the xand y-directions, using a normal distribution with a standard deviation of 5 µm, for the three-layer structure. The  analyses show that the proposed sandwich design is very robust to the most relevant fabrication-related imperfections for the entire frequency range of interest.

III. FABRICATION AND ASSEMBLY
The proposed transition is fabricated using a silicon-oninsulator (SOI) micromachining process, where both the handle layer and device layer are etched using a deep-reactiveion-etching (DRIE) based on an advanced BOSCH process to obtain low sidewall roughness. The buried oxide (BOX) isolation layer serves as an etch-stop layer; thus, both top and bottom waveguide faces have a very smooth surface resulting in low losses [8], [30].
As shown in Fig. 5, the SOI wafer (3-µm BOX layer, 275-µm handle layer, and 30-µm device layer) coated with a 2-µm thermal SiO 2 layer on both sides. As the first step, the mask is patterned on both sides of the wafer by means of lithography and oxide dry etching. Afterward, the handle and device layers are etched down to the BOX layer in two steps (first, the top side is etched then the wafer is flipped over, and the bottom side is etched as well). A dry etching process is later used in two steps for the top and bottom sides to remove the oxide hard masks and the BOX layer. Then gold metallization has been performed in a sequence of twostep spurting a 50-nm-thick titanium-tungsten (TiW) adhesion layer and then sputtering 1.5-µm gold. This sequence is carried out on both the top and bottom sides separately to coat all sides of the wafer. The average surface roughness achieved using this method is about 2.14 nm for the top/bottom of the waveguide, and 163.13 nm for the waveguide sidewalls [30]. Finally, the three metalized layers are vertically stacked in the desired order with the aid of predesigned precise Vernier scale alignment marks and vacuum holes on chips. Alignment is carried out manually based on [31] by using the vacuum and the Vernier scale marks placed in the corners of the chips. This method allows misalignment to be tracked and adjusted. The chips are assembled using thermo-compression bonding [32].

IV. MEASUREMENTS AND ANALYSIS
The conventional method of measuring silicon chips containing micromachined waveguides is to insert the silicon chip into a CNC-milled fixture with standard waveguide interfaces [31], [33], [34]. However, for sub-THz/THz frequencies, not matching fabrication tolerances and surface nonuniformities of the metal fixture, as compared to the more accurately Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply. manufactured silicon chips, resulting in interface problems. To avoid CNC-milled fixtures or interposers, an on-chip waveguide-flange interface is required to provide axial port configuration for the two device ports which allow the chip to be placed directly between the flanges of two test ports. Twoport S-parameters of the fabricated devices are measured using the ZVA-24 vector network analyzer (VNA) and Rohde & Schwarz ZC330 frequency extenders for 220-330 GHz. Fig. 6 shows the circuit configuration used to characterize the proposed twist. An on-chip axial transition is employed to guide the wave from the out-of-plane direction to the H-plane waveguide port (TE 10 port of the 90B:-twist). The axial transitions consist of two E-plane bends established in three layers which transfer the waves from out-of-plane to in-plane while isolating the input and output [17]. Two of the proposed 90 • -twist transitions are connected to the H-plane waveguide outputs of the axial transitions with a subsequent E-plane waveguide section between them to close the circuit loop. The closed-loop circuit consists of three E-plane waveguides and four E-plane 90 • bends. It should be noted that any designed E-plane waveguide device can be placed on the chip instead of the circuit loop.
The response of the proposed transition needs to be deembedded from the measured data. A two-tier calibration utilizing two sets of on-chip Thru-Reflect-Line TRL calibration kits [6], [7] is utilized for determining the S-parameters of the twist transition. One calibration kit (TRL H ) has its reference plane at the input of the characterized TE 10 -to-TE 01 transition, corresponding to the port with the TE 10 mode, while the other (TRL E ) has its reference plane at the output of the transition (port with TE 01 ). Both calibration kits are cofabricated on the same wafer. Fig. 7 shows microphotographs of the siliconmicromachined TRL H and TRL E calibration kits during the assembly when the first layer and the second layer have been vertically stacked and aligned.
The first calibration step is to use the TRL H and do the routine calibration for the T E , R E , and L E standards as DUTs. The first calibration removes the errors caused by the axial transitions from TRL E and shifts the reference plane to the twist's input. In other words, the results of the performed TRL H calibration are S-parameters of a new calibration kit TRL En which are a cascade of S-parameters of the proposed transition and S-parameters of the standards. The second step is to calibrate one of the previous step's outcomes as a DUT  with TRL En ; here, we used S-parameters of L En . The error of the second calibration results in the S-parameters of the proposed on-chip twist. The measured S-parameters of the de-embedded proposed 90 • -twist transition are shown in Fig. 8(a). The insertion loss is less than 0.2 dB with a return loss of better than 16 dB in the entire 220-325-GHz band (better than 23 dB in 223-305-GHz range). There is a good agreement between measurement and simulation results. The visible ripples in the measures S-parameters are a result of TRL calibrations that use a Thru standard with nonzero length instead of ideal Thru [35]. The measured S-parameters of the transition from port A to the H-plane waveguide (input of the twist) are shown in Fig. 8(b); the extracted results are in excellent agreement with the ones reported earlier in [17].
A comparison between the performance of the proposed twist and other recently published transitions in the sub-THz frequency range is summarized in Table II. V. LOWPASS FILTER An LPF is designed and integrated with the proposed 90 • -twist transition to demonstrate the application of the platform. Traditionally, LPFs are designed through an L-C ladder network, which, in rectangular waveguides, is implemented by capacitive irises and inductive waveguide sections having lengths shorter than a quarter wavelength. The capacitive irises are attached to the top and bottom walls of the waveguide; therefore, their fabrication in silicon micromachining is much simpler using the orthogonal orientation of the waveguide, as etching is carried out vertically. Due to this fact, the proposed orthogonal orientation platform is an enabling technology for silicon micromachined LPFs.
For the demonstrator filter, a cutoff frequency f max of 280 GHz and a return loss R L of 20 dB have been chosen as design specifications. The design of the LPF, consisting of ten sections of the three-layer uniform silicon micromachined E-plane waveguide separated by nine capacitive irises, is shown in Figs. 9(a) and (b). The reference planes are located at the input and output irises. Fig. 9(c) shows a microphotograph of the top and the middle layer of the LPF before assembly. The LPF is characterized using an on-chip TRL calibration kit integrated on the same chip as the LPF. The de-embedded measured results are shown in Fig. 10(a), along with the simulated, which are in good agreement. The average insertion loss in the passband is 0.4 dB, and the return loss is better than 14 dB. Fig. 10(b) shows measured and simulated S-parameters of the LPF together with connected input and output twists. Fig. 10(c) shows the measured and simulated S-parameters of the whole structure before deembedding, containing the axial transition, both twists, and the LPF. In our design, the performance of the LPF (the external and internal couplings) is optimized without considering the twist and axial transition. However, the dimensions can be reoptimized to achieve the desirable performance of the LPF with the twists and axial transitions connected.

VI. CONCLUSION
We have presented a low-loss compact platform enabling cofabrication and on-chip connection of orthogonal waveguide subsystems using a novel silicon-micromachined 90 • rectangular waveguide twist with simple and compact geometry. The structure has been fabricated in three gold-metalized silicon chips bonded together. A sensitivity analysis of the assembly imperfections has been performed, and the effects of underetching have been studied. A good agreement between simulation and measurement results has been achieved. The experimental results have shown a 23-dB return loss in most of the operation bands (223-305 GHz). A two-tier calibration method using two sets of TRL calibration kits has been employed to de-embed the proposed twist's S-parameters. The proposed solution enables on-chip interconnection and simple integration of the H-and E-plane waveguide networks in the subterahertz range, including LPFs. For the first time, a silicon micromachined LPF with a cut-off frequency of 280 GHz has been fabricated and directly measured on a flange with the aid of the proposed platform. The LPF has shown an excellent performance throughout the entire band of operation.