Characterization and Advanced Modeling of Dielectric Defects in Low-Thermal Budget RMG MOSFETs Using 1/f Noise Analysis

This study presents a comprehensive investigation of defects in the gate-stack of low-thermal budget replacement metal gate (RMG) MOSFETs treated with novel dielectric passivation techniques using 1/<inline-formula> <tex-math notation="LaTeX">${f}$ </tex-math></inline-formula> noise characterization and advanced modeling. This research demonstrates that MOSFETs with gate-stacks treated with atomic hydrogen (H*) and oxygen (O*) (T < 450 °C) yield 1/<inline-formula> <tex-math notation="LaTeX">${f}$ </tex-math></inline-formula> noise levels comparable to those of high-thermal budget devices. We also demonstrate that the noise of both pMOSFETs and nMOSFETs mainly originates from defects in the SiO2 interfacial layer (IL). In addition, accurate modeling of 1/<inline-formula> <tex-math notation="LaTeX">${f}$ </tex-math></inline-formula> noise provides useful insights into the dielectric defect densities before and after passivation. Notably, the contribution of O-vacancies in HfO2 to 1/<inline-formula> <tex-math notation="LaTeX">${f}$ </tex-math></inline-formula> noise appears negligible, whereas it is very important for positive bias temperature instabilities (PBTIs). The results confirm the effectiveness of H* and O* treatments in reducing the electrically active dielectric defects while contributing to a better understanding of the underlying passivation mechanisms.

Abstract-This study presents a comprehensive investigation of defects in the gate-stack of low-thermal budget replacement metal gate (RMG) MOSFETs treated with novel dielectric passivation techniques using 1/f noise characterization and advanced modeling.This research demonstrates that MOSFETs with gate-stacks treated with atomic hydrogen (H*) and oxygen (O*) (T < 450 • C) yield 1/f noise levels comparable to those of high-thermal budget devices.We also demonstrate that the noise of both pMOSFETs and nMOSFETs mainly originates from defects in the SiO 2 interfacial layer (IL).In addition, accurate modeling of 1/f noise provides useful insights into the dielectric defect densities before and after passivation.Notably, the contribution of O-vacancies in HfO 2 to 1/f noise appears negligible, whereas it is very important for positive bias temperature instabilities (PBTIs).The results confirm the effectiveness of H* and O* treatments in reducing the electrically active dielectric defects while contributing to a better understanding of the underlying passivation mechanisms.

I. INTRODUCTION
T HE introduction of 3-D stacking techniques for MOSFETs is envisioned in the CMOS scaling roadmap to enable higher device density and improved functionality within the area footprint [1], [2], [3].Two integration schemes are mainly used for high-κ/metal gate-stacks: gate-first (often referred to as MIPS, "metal-inserted poly-Si") and gatelast (also called RMG, "replacement metal gate") [4].The terminologies "first" and "last" refer to whether the gate electrode is deposited before or after the high-temperature S/D doping activation anneal(s) of the flow.Focusing on the RMG process, two main alternatives are possible for 3-D stacking: sequential [5], [6] and monolithic [7] integration.In sequential 3-D integration, a fresh slab of Si is attached by oxide-to-oxide bonding on top of a bottom device tier to fabricate a top device tier with nanometric alignment to the bottom counterpart.In such scheme, the top-tier device needs to be fabricated at a reduced thermal budget (typically max T < 550 • C) to preserve the integrity of the bottom device.Conventionally, high-temperature anneals are performed to passivate dielectric defects [8]; these high-T processes are not compatible with top tier fabrication, posing concerns over the reliability and noise of the device.Moreover, gate-stacks with a reduced thermal budget would be beneficial also for complementary field-effect transistor (CFET) monolithic integration [7], since in this integration flow the contacts of the bottom device are already in place during the RMG flow and their performance might degrade at higher temperatures.
To solve this issue, novel dielectric passivation techniques involving hydrogen (H*) and oxygen (O*) radicals at low-thermal budgets (T < 450 • C) have been recently proposed [9], [10].These techniques have shown BTI reliability in line with devices fabricated with high-thermal budget processes.However, the noise of these low-thermal budget devices has not been experimentally evaluated so far.
In this article, we characterize and model the defects in low-thermal budget RMG MOSFETs through 1/f noise experiments and exploit advanced noise models for the interpretation of the results.This analysis further proves the ability of the H* and O* treatments to passivate dielectric defects and gives additional physical insights into the defects involved in the passivation.This article proceeds as follows: Section II introduces the measurement setup and the devices considered in this study.Section III shows the measurement results and the main implications.Section IV describes the interpretation of the experimental data with comprehensive models Finally, the concluding Section V summarizes the main results.

II. MEASUREMENT SETUP AND DEVICES
We considered planar nMOSFETs and pMOSFETs with W = L = 1 µm, SiO 2 /HfO 2 as gate dielectrics, and Ti-based metal gates.The source and drain of these test devices consist of highly doped Si regions without any strain booster technology.The devices have been fabricated with the same RMG process but different annealing techniques and thermal budgets, as listed in Table I.In particular, atomic hydrogen (H*) anneals of the SiO 2 interfacial layer (IL) and atomic oxygen (O*) anneals of the high-κ dielectric (HK) [11] are compared and combined.The values of equivalent oxide thickness (EOT) and effective work function (eWF) in Table I are obtained by calibrating a Schrödinger-Poisson solver to the experimental C-V curves [12], [13] (not shown here).
For the pMOS, we measured devices with low-thermal budget processes without any annealing (i.e., as-deposited), treated with "mild" H* (where the exposure to atomic hydrogen has been limited to avoid excessive EOT increase related to the desorption of OH-groups from the IL [9]), treated with H*, or with both H* and O*.The same goes for the nMOSFETs, where an O*-only case replaces the case with "mild" H* of the pMOSFET.In addition, we measured both nMOSFETs and pMOSFETs devices treated with a high-temperature postdeposition anneal (PDA) at 850 • C (done after the high-κ dielectric deposition and before the gate metal deposition) to have a direct comparison with devices with standard high-thermal budget processing.Apart from this latter case, all the other gate-stacks have a maximum process temperature of 450 • C, in line with 3-D integration requirements.
All the pMOSFETs use the same p-work function metal (WFM, TiN), while the nMOSFETs use an n-WFM based on TiAl, except for the nMOSFET subject to high-T PDA, which uses a midgap WFM [resulting in slightly higher V T ; see Fig. 1(a)].The midgap WFM is obtained by modifying the thickness of the bottom TiN and TiAl metal layers in the n-WFM gate metal stack in line with industry practice [14].The eWF values are reported in Table I.Note that each annealing scheme induces some eWF changes, as discussed in [9] and [10], due to the passivation of "fixed" charge in the dielectrics; nevertheless, the pMOS and nMOS V T s remain in a range compatible with CMOS integration requirements in all the cases (Fig. 1).All the devices were subject to a conventional sintering anneal at the end of the fabrication flow, at 420 • C for 20 min in forming gas.
We used a Keithley B1500 and a Keysight low-frequency noise analyzer to perform the dc and noise characterization at a controlled temperature of 25 • C.Moreover, we kept the drain voltage (|V DS |) equal to 50 mV during the noise measurements to bias the devices in the linear regime.

III. MEASUREMENTS AND DISCUSSION
This section presents the experimental results, beginning with the I -V measurements, followed by the characterization with 1/f noise.I.The threshold voltage V T is extrapolated from the linear I D − V G S curve at the point of maximum transconductance [15], while the SS is extracted by taking the median value of SS in the 0.1-100-nA drain current range.Extensive performance and reliability assessment of these devices, including the I ON and I OFF values, can be found in [11].

A. I-V Curves
For the nMOS, we note that the low-temperature H* treatment improves the subthreshold swing (SS) with respect to the "as-deposited" case, reaching a value of 66 mV/dec that is in line with the PDA device with a high-thermal budget.This suggests that the H* treatment passivates defects that affect the SS of the "as-deposited" devices.The threshold voltage shifts between nMOSFETs with different treatments are mostly attributed to the changes in EOT (see Table I), variation in trapped charge inside the dielectrics after passivation, and, for the nMOSFET with PDA, the different gate metal work function.
When looking at the pMOSFETs, the low-thermal budget devices have SS values in line with the high-thermal budget PDA device.Moreover, we do not observe significant changes in the SS with the treatments.This suggests that low-thermal budget dielectrics do not have a sufficient number of defects in the energy range that can be probed by monitoring the subthreshold swing variation in pMOSFETs [16], especially considering the limited SS sensitivity to defects in gate-stacks with extremely scaled EOTs.However, we note that the H* treatment introduces a threshold voltage shift with respect to the as-deposited case.This is ascribed to the passivation of defects in the SiO 2 interlayer reducing the fixed charge in the dielectric [9].In addition, there is a component of threshold voltage shift related to the change in EOT and the introduction of the O* treatment.Nevertheless, the threshold voltages after H* and O* treatments are in a range that is compatible with CMOS technology requirements.

B. 1/f Noise
We now evaluate the effect of the various passivation treatments on the drain current noise of the device.To interpret the measured power spectral density, we consider the well-known expression for the input-referred drain current noise [17] where S id is the power spectral density of the drain current noise, g m is the transconductance, µ eff is the effective mobility, N BT is an effective dielectric trap density per unit volume and unit energy, α is a tunneling coefficient estimated through the Wentzel-Kramers-Brillouin (WKB) approximation, C ox is the effective gate dielectric capacitance per unit area, q is the elementary charge, T is the temperature, f is the frequency and α sc is a parameter related to mobility fluctuations (MF).More accurate and complete models for 1/f noise will be used in Section IV.Equation (1) allows us to discriminate between carrier number fluctuations (CNFs) and MF by looking at the drain current dependence of the S vg .Our analysis will focus only on CNF since MF could be caused not only by dielectric defects [18], [19].On the other hand, in the CNF theory [18], 1/f noise in the drain current is attributed to charge fluctuation in dielectric traps.Therefore, the analysis of 1/f noise in the CNF region is a powerful tool to evaluate the quality of dielectrics and to monitor their degradation/improvement after stress/treatments.Fig. 2 shows comparison of the measured S vg spectra of nMOS (a) and pMOS (b) devices with different annealing techniques at V G S − V T = V ov = 0 V.The noise spectra follow a 1/f dependence and do not show any white noise contribution, which could originate from trap-assisted tunneling (TAT) leakage current in the gate flowing toward the drain or thermal noise.Moreover, the noise of the devices treated with the low-thermal budget H*-O* treatments is comparable to the one with high-temperature PDA and significantly lower than the devices with the dielectrics "as-deposited."Note that S vg also has a strong dependence on C ox [see (1)].Thus, the noise reduction observed in Fig. 2 appears smaller than the actual reduction in the trap densities N BT derived from (1), primarily due to minor variations in the EOT of the devices.
The 1/f noise in the CNFs regime (α sc µ eff C ox I D /g m ≪ 1) is proportional to the effective trap density N BT inside the dielectrics This quantity represents an effective trap density since it does not take into account the spatial sensitivity of noise to the dielectric trap fluctuations and the trapping/detrapping events involving the gate electrode [20], [21], [22].However, despite these limitations, S vg in the CNF regime can serve as a monitor of the quality of gate dielectrics, particularly when comparing devices with similar gate-stacks (i.e., same gate metals and as-deposited dielectric thicknesses), as it is in our study.Note that (1) gives no dependence on I D in the CNF regime if we assume that the distribution of the dielectric traps probed by the noise does not vary much for different biases (i.e., different energy alignment between the Fermi levels of the carrier reservoirs and the dielectric trap energy levels).
To see whether a given bias point falls in the CNF regime, we plot in Fig. 3 S vg • f (which is essentially constant versus frequency since S vg goes as 1/f ) against I D .For the nMOSFETs, there is a range of bias points where we see almost no dependence on I D [Fig.3(a)].On the other hand, it is difficult to identify such a range of biases for the pMOSFETs [Fig.3(b)].However, we note that S vg curves tend to flatten out going toward the points at low currents.In the following, we will use the data at the lowest currents in Fig. 3 (which correspond to V ov = 0 V) to extract an effective N BT with (2), assuming the devices operate in the CNF regime.
Note that the increase in S vg with drain current has been extensively observed [23] and it can be fit with an α sc µ eff coefficient of about ≈10 6 cm 2 /C, consistently with [23].However, there is a strong debate on the underlying cause of noise in this region, and it could be due not only to dielectric traps [18], [19].For this reason, we are not extracting N BT from the noise points falling in this region.
The N BT values extracted with (2) at V ov = 0 V (the points at lowest current in Fig. 3) are presented in Fig. 4 for both nMOSFETs and pMOSFETs with the different annealing treatments of Table I.The effective N BT for both nMOS and pMOS is significantly reduced with the introduction of the H* low-thermal budget treatment (approximately 27x for the nMOS and 4x for the pMOS) and essentially unaffected when O* is also inserted (although a 4x reduction can be observed in the nMOS case with O* treatment alone).Since  the H* treatment is applied only on the SiO 2 IL before HKMG deposition, we deduce that the noise in both "as-deposited" nMOS and pMOS is dominated by defects present in the interlayer.This is not surprising for the pMOS since it is expected that the defects in SiO 2 are the main cause for 1/f noise [24] and negative bias temperature instabilities (NBTIs) [25].On the contrary, the noise of nMOS with the standard HKMG stack has been attributed to the O-vacancies in HfO 2 [24] which is also the main cause of positive bias temperature instabilities (PBTIs) [26].Instead, this study shows that the main cause for 1/f noise in nMOSFETs with low-thermal budget are the defects in SiO 2 , as it is for pMOSFETs.Fig. 5 shows plots of the equivalent N BT extracted through 1/f noise measurements using (2) against the EOT for all the devices in Table I.Fig. 5 reports also the results for reference metal-inserted poly-Si (MIPS) stack (also known as gate first) devices with the highest possible thermal budget (note that in this legacy integration scheme, the final gate-stack is fabricated before the S/D implants, and therefore, it is exposed to the doping activation anneal at T in the range of 1000-1100 • C).The MIPS have the best results in terms of scaled EOT and low N BT , as expected [27], since the gate-stack is exposed to an additional high-temperature anneal.However, the low-thermal budget processes with H* give comparable results and even outperform the high-T PDA process.N BT of the combined H*-O* process is very competitive, although the penalty in EOT given by the O* process is large.Further optimization of the process is needed to obtain competitive EOT values.I.The stars refer to MIPS stack devices with high-thermal budget process.

IV. ADVANCED MODELING OF DIELECTRIC DEFECTS
WITH 1/f NOISE Equation ( 2), used in the previous section for trap density extraction, is not accurate when applied to thin dielectric gate-stacks.This is due to several approximations, including the neglect of trapping/detrapping events involving the gate metal [20], [21], [22].
In this section, we consider the comprehensive noise model of [20], [21] for S vg to interpret the data and reveal the effect of the low-thermal budget treatments on the defects in the dielectrics.The model implements the complete trapping/ de-trapping dynamics for the CNF input-referred drain current noise in MOSFETs biased in the linear region of operation [20], [21] where z is the direction perpendicular to the channel, f T = f T (E T , z T ) is the function describing the occupation of the dielectric traps, τ = τ (E T , z T ) is the trapping/detrapping time implemented according to the nonradiative multiphonon (NMP) model [28], N BT = N BT (E T , z T ) is the dielectric trap density per unit volume and energy, and is an electrostatic scaling factor that takes into account the relationship between charges fluctuating in the dielectric and charges fluctuating in the channel [20].This model can take into account the effect of charge trapping/detrapping with the gate metal and the term K (z T ), both very important for thin dielectric gate-stacks [22].
The computation of the trapping/detrapping time τ includes both quantum mechanical tunneling and thermally activated capture/emission processes (see NMP model of [28]).Moreover, it requires information on the alignment between the Fermi levels of the carriers reservoir (channel and gate) with the bands of the dielectrics and the electric field inside the dielectrics.To extract these quantities, we used 2-D TCAD simulations in Synopsys Sdevice [29] of bulk MOSFETs with the density gradient model for the quantization effects and with the technological details of Table I.
The traps' distributions N BT and the relaxation energies used in (3) for SiO 2 and HfO 2 are based on ab initio Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
calculations [30] and BTI measurements [10], [31].We use Gaussian distributions in energy to model N BT .Moreover, we consider the traps in HfO 2 uniform in space, while we consider the traps in SiO 2 exponentially decaying starting from the interface with the silicon with a decay length σ z T = 0.5 nm.This is done to reproduce the increased number of defects due to the strain at the Si/SiO 2 interface [9].The expression used for different contributions to N BT is then where µ E T (z) is the mean energy of the Gaussian distribution with the midgap of the silicon as a reference at zero band bending, σ E T is the standard deviation, E T is the energy of the trap, z T is the position of the trap, z 0 is the coordinate of the Si/SiO 2 interface, and σ z T is the exponential decay length in space.In the case of uniform distribution, we have σ z T → +∞.
According to the measurement results shown in Fig. 4, the noise in both nMOS and pMOS is strongly reduced after H* treatment to the interlayer.This is a strong indication that the dominating defects for 1/f noise in the case of dielectrics without any passivation are found in the SiO 2 interlayer.Moreover, we know that the SS of the nMOS is improved with H* treatment, while the SS of the pMOS remains essentially unvaried after the treatments.The variation in SS with different passivation treatments should reflect the variation in near-interface defects with energy going from the midgap to the conduction/valence band.
Following these indications, we inserted two defect bands in SiO 2 , one closer to the conduction band and one closer to the valence band with the parameters listed in Table II.The H* treatment reduces the total number of traps in both these defect bands, as shown in Table II and Fig. 6(a).The trap distributions used for SiO 2 shallow and deep traps are in good agreement with the hydroxyl-E' (H-E') defect distributions obtained from ab initio studies [30], which identify the H-E' defect to be more likely present with high concentrations in SiO 2 , and its energy distribution could contribute to both NBTI (in pMOS) [10] and 1/f noise (in both pMOS and nMOS).An H-E' defect can form in SiO 2 whenever a hydrogen atom attaches to and eventually breaks a strained Si-O bond, forming an hydroxyl group.
For HfO 2 , we inserted deep traps that are accessible through the Fermi level of the gate metal with a pWF (therefore, only in the pMOS devices) [31] and an O-vacancies' distribution with a very high concentration based on PBTI model calibrations [10] [see Fig. 6(b)].
The band diagrams of both p-type and n-type MOSFETs with the defect bands of Table II are depicted in Fig. 7.Only traps aligned with the Fermi level of the channel or the gate contribute to 1/f noise.Therefore, n-type and p-type MOSFETs are sensitive to different defect bands in the dielectric, and the various passivation treatments will affect their noise in a distinct way.Note that the O-vacancies never    II.
for PBTI) are not contributing to 1/f noise in either pMOS or nMOS.
Fig. 8 shows comparison of the predictions of (3) using traps' distributions of Table II to the noise measurements at V ov = 0 V.The excellent agreement between (3) and the noise measurements confirms that the proposed defect bands and the reduction in their amplitude with the various treatments assumed in our study are fully consistent with the measured noise spectra.
Note that the noise spectra in Fig. 8 have an uncertainty of a factor 2-3. Therefore, the values in Table II feature similar uncertainties.However, the fitting considers the average value of S vg • f along the measured frequency range.The averaging process over frequency should effectively reduce the uncertainty on the hypothesis that this is equally distributed among points at different frequencies.Moreover, S vg variations observed after applying the passivation treatments are higher than those uncertainties.defects in HfO 2 fluctuates through charge trapping/detrapping with the pWF gate electrode.Therefore, their contribution depends on the work function of the gate metal.This explanation is consistent with the asymmetric reduction in noise seen in Fig. 4 (27x for the nMOSFET and 4x for the pMOSFET).

V. CONCLUSION
We measured planar MOSFETs with low-thermal budget RMG gate-stacks with or without low-temperature treatments using atomic hydrogen (H*) and/or oxygen (O*) and showed their effect on the dc and 1/f noise characteristics.We demonstrated that the low-thermal budget passivation treatments with atomic hydrogen (H*) and oxygen (O*) decrease the 1/f noise down to a level competitive with high-thermal budget devices.Extensive comparison with an advanced model of 1/f noise led us to identify the defects in SiO 2 (identified as H-E' defects) as the main cause of 1/f noise in both nMOSFETs and pMOSFETs when the dielectric is not passivated with high-temperature anneals or dedicated radical treatments.After passivation, the noise of the nMOSFETs is still dominated by H-E' defects, while the noise of the pMOSFETs starts to be dominated by deep traps in HfO 2 that are accessible through the pWF gate metal.

Fig. 1 .
Fig. 1.I D versus V GS for (a) nMOSFETs and (b) pMOSFETs with the parameters of Table I and |V DS | = 50 mV.

Fig. 1
shows comparison of I D − V G S at |V DS | = 50 mV for both the nMOSFETs (a) and the pMOSFETs (b) described in Table

Fig. 4 .
Fig. 4. Equivalent N BT extracted from 1/f noise according to (2) versus the different passivation treatments analyzed in this work for (a) nMOSFETs and (b) pMOSFETs.

Fig. 5 .
Fig. 5. Equivalent N BT extracted from 1/f noise according to (2) versus EOT for the nMOSFETs (full symbols) and pMOSFETs (open symbols) listed in TableI.The stars refer to MIPS stack devices with high-thermal budget process.

Fig. 6 .
Fig. 6.Plot of the trap energy density distributions N BT in SiO 2 (a) and HfO 2 .(b) Energy is referenced to the silicon midgap energy.

Fig. 7 .
Fig. 7. Sketch of the energy band diagrams of both n-type and p-type MOSFETs with the defect bands of TableII.
The 1/f noise of the nMOSFETs after H*-O* or PDA passivation is caused by the residual H-E' defects in the SiO 2 .On the other hand, the noise of pMOSFETs after H*-O* or PDA passivation is caused by the deep defect band in HfO 2 , because the IL defect density has been suppressed by H* treatment, and the O-vacancy band in HfO 2 , passivated by O* anneal, does not contribute to noise.The occupation of deep

Fig. 8 .
Fig. 8.Comparison between S vg predicted by (3) with the trap distributions of Table II against measurements at V ov = 0 V for (a) nMOSFETs and (b) pMOSFETs.

TABLE I PARAMETERS
OF THE DEVICES CONSIDERED IN THIS ARTICLE of 1/f noise providing insights on the defect passivations.

TABLE II ( a )
ENERGY DISTRIBUTIONS OF THE DEFECT BANDS IN THE DIELECTRICS.THE SAME ENERGY DISTRIBUTIONS ARE CONSISTENTLY USED TO MODEL THE NOISE RELATIVE TO THE DIFFERENT PASSIVATION TREATMENTS CONSIDERED.ALL ENERGIES ARE REFERRED TO THE SI MIDGAP.NOTE THAT THE DEFECTS IN SIO 2 ARE EXPONENTIALLY DISTRIBUTED IN SPACE WITH THE CENTER AT THE INTERFACE WITH THE CHANNEL AND σ Z T = 0.5 NM, WHILE THE DEFECTS IN HFO 2 ARE ASSUMED UNIFORM IN SPACE.(b)VALUES OF PEAK TRAP DENSITY N BT 0 FOR DIFFERENT TREATMENTS.DIFFERENCES WITH RESPECT TO THE "AS-DEPOSITED" VALUES ARE IN BOLD.NOTE THAT IN THE MODEL THE CONCENTRATION OF O-VACANCIES IN HFO 2 IS NOT VARIED WITH THE TREATMENTS BECAUSE THESE DEFECTS ARE NOT PROBED WITH 1/f NOISE SO THE VARIATIONS CANNOT BE ESTIMATEDcontribute to the 1/f noise due to energy misalignment with Fermi levels of the channel and gate metal.The O* treatment should strongly reduce the number of O-vacancies in HfO 2 , but this cannot be probed with 1/f noise because their energy alignment with the Fermi levels does not allow them to fluctuate during the measurements, not even in the case of dielectrics where only SiO 2 has been passivated.This is a strong indication that O-vacancies in the HfO 2 (important