Back-End-of-Line-Compatible Fin-Gate ZnO Ferroelectric Field-Effect Transistors

We report the back-end-of-line (BEOL)-compatible 3-D oxide semiconductor (OS) fin-gate ferroelectric field-effect transistors (Fe-FETs) featuring atomic layer deposition (ALD)-grown zinc oxide (ZnO) channel and Zr-doped HfO2 (HZO) ferroelectric dielectric. Both ZnO and HZO are able to conformally cover the fin-shaped tungsten (W) metal gate with uniform thickness on all surfaces. With the optimization of ALD for the growth of the ZnO channel film and extensive gate-stack engineering, our ZnO Fe-FETs show excellent electrical characteristics, including memory windows (MWs) of 1.9 and 1.5 V with the channel length (<inline-formula> <tex-math notation="LaTeX">${L}_{\text {ch}}$ </tex-math></inline-formula>) of <inline-formula> <tex-math notation="LaTeX">$1~\mu \text{m}$ </tex-math></inline-formula> and 50 nm, respectively, the high endurance of <inline-formula> <tex-math notation="LaTeX">$10^{{8}}$ </tex-math></inline-formula> cycles, long-term retention of more than ten years at room temperature, robust ON/OFF ratio of more than six orders, and good linearity of the multistate conductance characteristics. Together with the capability to suppress the device-to-device threshold voltage (<inline-formula> <tex-math notation="LaTeX">${V}_{\text {th}}$ </tex-math></inline-formula>) variation due to the unique fin-gate structure, our devices demonstrate tremendous potential for future ultrahigh-density 3-D integrated computing applications.

traditional von Neumann architecture suffers from increased power dissipation and the performance gap between the memory and processing units, incapable of meeting future needs [1], [2]. Fortunately, the concept of in-memory computing was presented in which the memory itself can be the computing unit, leading to the alleviation of the heavy data communication between the processor and the memory hierarchy [3], [4]. One attractive direction to realize in-memory computing is the employment of emerging nonvolatile memories (NVMs) with proper periphery circuits to enhance speed, density, and power efficiency [5], [6], [7]. Among all the NVMs, such as resistance switching random access memory (RRAM) [1], phase-change memory (PCM) [8], or magnetoresistive RAM (MRAM) [9], ferroelectric field-effect transistors (Fe-FETs) not only promise to deliver the fast write speed, fast, and nondestructive readout, but also enjoy the benefit of lowenergy switching due to the field-driven switching mechanism [10], [11], [12]. Furthermore, as three-terminal devices, the cell and circuit design of Fe-FETs are similar to those of conventional transistors. The use of HfO 2 -based ferroelectric dielectrics makes the Fe-FETs highly adaptable to advanced CMOS technology [13].
Recently, oxide semiconductors (OSs) have attracted great attention as the channel materials of Fe-FETs [14], [15], [16], [17], [18], [19], [20], [21], [22], [23]. Compared to the amorphous Si FETs, OS FETs generally have higher mobilities (>10 cm 2 ·V −1 ·s −1 ) while keeping a back-end-ofline (BEOL)-compatible process thermal budget for monolithic 3-D integration [24], [25]. Additionally, to optimize the device density in the limited footprint area of integrated circuits, devices with a 3-D structure are highly desired where the atomic layer deposition (ALD) technique for thinfilm deposition would be required [26], [27]. Compared to the conventional sputtering techniques, ALD features the high controllability of the film thickness and the conformal coverage of the 3-D structures, bringing new opportunities for high-density integrated chips. Despite this, a grand challenge that is yet to be addressed is the realization of 3-D OS Fe-FETs with excellent device performance that could endow further device downscaling and device density upscaling. In this study, we propose and experimentally realize the BEOL-compatible 3-D zinc oxide (ZnO) Fe-FETs with a fin-shaped gate surrounded by highly uniform and conformal ALD-deposited Zr-doped HfO 2 (HZO) gate dielectric and ZnO channel. With proper process optimization guided by deep materials analysis, our ZnO Fe-FETs could deliver decent electrical and memory characteristics using a metalferroelectric-semiconductor (MFS) structure without the need of employing a floating metal gate [28]. Extensive characterizations were carried out to show that 3-D fin-gate ZnO Fe-FETs are able to achieve comparable performance to the planar devices in terms of memory window (MW), endurance, retention, and multistate linearity. Moreover, the proposed fin-gate ZnO Fe-FETs help to suppress the threshold voltage (V th ) variation at a fixed device footprint when compared with the planar counterparts, paving the way for future ultrahigh-dense 3-D integrated computing applications. Initial results were reported in [39], and this article provides an extension with more comprehensive and detailed information.

II. DEVELOPMENT AND OPTIMIZATION OF ZNO FETS
A. ALD of ZnO Thin Films for ZnO FETs Fig. 1(a) illustrates the schematic of the ALD process of the ZnO thin film. C 4 H 10 Zn (DEZ) and H 2 O are precursors for Zn and O, respectively. To ensure the high quality of the ZnO film, consecutive DEZ pulse (200 ms) and H 2 O pulse (100 ms) were adopted, followed by a purging time of 10 s between the different precursors. Fig. 1(b) shows the growth rate per cycle of the ZnO thin film at different temperatures, and a higher deposition rate can be observed at lower temperatures. Besides, to evaluate the quality of ZnO thin films, the refractive index is used as an indicator, as demonstrated in Fig. 1(c). A maximum refractive index of 1.97 at 632.8 nm can be observed for the ZnO film deposited at 150 • C, indicating that a higher atomic density and lower hydrogen doping degree can be achieved at this ALD temperature [29]. It has been reported that ALD temperatures higher than 200 • C provide thermal activation  energy that could result in high -OH doping concentration in the ZnO film [30], [31]. In this case, it would trigger higher defect concentrations, which can serve as traps in the ZnO film, thus undermining carrier mobility [32]. Here, we focus on two ALD temperatures, that is, 150 • C and 200 • C, for the following optimization of ZnO thin films.
The staggered bottom-gate ZnO FETs were fabricated to evaluate the ZnO characteristics at the device level. Fig. 2(a) illustrates the schematic of the ZnO FETs. The detailed fabrication process can be referred to [33]. Here, the channel/dielectric stack consists of 8-nm ZnO and 10-nm HfO 2 . The channel length (L ch ) is 5 µm, and all devices were annealed in N 2 at 350 • C after the device fabrication. Fig. 2(b) shows the typical transfer characteristics of the ZnO FETs with the two deposition temperatures when the drain voltage (V D ) is 0.1 V. Both types of FETs show a high ON/OFF ratio of more than six orders, while the hysteresis of 150 • C ALD-grown ZnO FETs is slightly smaller than that of 200 • C ALD-grown ZnO FETs. Fig. 2(c) and (d) shows the transconductance (G m ) and field-effect mobility (µ FE ) of two types of FETs, respectively. The peak G m at V D = 0.1 V increases from 0.22 to 0.30 µS/µm as the ALD temperature of ZnO decreases from 200 • C to 150 • C, and the 150 • C ALD-grown ZnO FETs also show a higher µ FE of 8.76 cm 2 ·V −1 ·s −1 when the carrier density (N carrier ) is 1.5 × 10 13 cm −2 , compared to that of 200 • C ALD-grown ZnO FETs (6.98 cm 2 ·V −1 ·s −1 ). Therefore, 150 • C is selected as a desirable ZnO deposition temperature for further study.

B. Effects of Thermal Annealing on ZnO FETs
In addition to the proper ALD temperature, thermal annealing is regarded as an effective strategy to improve the device performance because the trapping level below the conduction band of ZnO can be optimized [34]. In this section, three different kinds of annealing ambient gases are investigated: 1) O 2 ; 2) N 2 ; and 3) forming gas (FG). Fig. 3 shows the atomic force microscope (AFM) images of ZnO thin films after being annealed in different ambient gases at 350 • C. The root-mean-square (rms) roughness of the ZnO thin film shows insignificant changes with different annealing conditions. Fig. 4 compares the transfer characteristics of the asfabricated and postannealed ZnO FETs under O 2 , N 2 , and FG at 350 • C. Compared to the pristine FETs, thermal annealing could generally improve the current and reduce the hysteresis, and on this basis, the proper annealing condition could further tune the device's performance. Table I summarizes the key parameters of FETs with different annealing ambient gases. Among the three types of gases, annealing in FG could result in a smaller subthreshold swing (SS) and a much lower hysteresis. Moreover, µ FE of FG-annealed ZnO FETs also increases to 10.8 cm 2 ·V −1 ·s −1 when N carrier is 2 × 10 13 cm −2 , indicating the improvement of the ZnO/HfO 2 gate-stack.
Furthermore, the positive bias stress (PBS) stability of the FG-annealed ZnO FETs was also evaluated. Fig. 5(a) illustrates the procedure of the bias stress test. First, an initial transfer curve (pre-I D V G ) was measured to obtain the pristine V th . Then, the stress and measurement periods were implemented alternately. During the stress period, the gate voltage (V Gstress ) and the drain voltage (V Dstress ) were set to be 3 and 0 V, respectively. The fast-I D V G measurement was used where the sweeping time of each I D V G curve was ∼310 µs to obtain a more accurate result. Fig. 5(b) shows the results of the PBS test. Here, two annealing temperatures are considered (350 • C and 400 • C), and some devices have undergone O 2 annealing before the FG annealing [solid symbols in Fig. 5(b)]. All devices show a positive V th during the PBS test, which can be attributed to the electrons trapping at the dielectric/channel interface or into the dielectric layer. Besides, among all the FG annealing conditions, it can be found that annealing at 350 • C gives a lower V th when compared with 400 • C-annealed conditions, and annealing in FG directly without annealing in the O 2 environment exhibits better PBS stability for ZnO FETs when compared with other conditions.
The photoluminescence (PL) spectra were also obtained to investigate the effect of annealing conditions on ZnO FETs. For the identification of defects in ZnO, we used a Gaussian model to fit and analyze each band in the visible light emission range, as shown in Fig. 6(a). The deep-level emission of the ZnO film comprises one yellow band at 2.04 eV and two sets of red bands at 1.66 and 1.83 eV. The former one is involved with the oxygen interstitial (O i ), and the latter ones are attributed to oxygen vacancy (V O ). Fig. 6(b) outlines the O i and V O levels at different annealing conditions. It indicates that N 2 or FG annealing could greatly reduce the O i and V O levels in ZnO. Fig. 6(c) illustrates the band diagram of the PL emission by using the full-potential linear muffin-tin orbitals method and the measured data. The band transition from zinc interstitial (Zn i ) to O i defect levels in ZnO produces the yellow band at 2.06 eV, and it can be deduced that the O i level is located approximately at 2.28 eV below the conduction band. Similarly, the energy transition from the V O energy level to either the top of the conduction band or valence band gives rise to the red emission at 1.66 and 1.82 eV, respectively. Hence, the V O level of ZnO is located at 1.66 eV below the conduction band.
Moreover, as the quality of the ZnO/HfO 2 bilayer is critical for the ZnO FETs, we analyzed the PL spectra of the ZnO/HfO 2 stack with different annealing conditions. The pristine ZnO/HfO 2 film exhibits larger PL intensity than either the ZnO or the HfO 2 individual film, whereas the annealed ZnO/HfO 2 film possesses a reduced PL intensity with the value between the two annealed components, as shown in Fig. 6(d). Because of the low contribution of HfO 2 in PL intensity, which can be neglected in contrast to that of the ZnO layer, the deep-level emission of ZnO/HfO 2 film has the same defect types, that is, O i and V O, as the ZnO film.  reduces sharply after annealing, especially when annealing in FG. It is worth noting that the V O and O i states can only be controlled to a very limited level for the ZnO annealing in the N 2 or O 2 environment. O 2 or N 2 annealing only deals with the oxygen-deficiency group on the very top specific surface or reforms O i in a very fixed region, followed by the inefficient diffusion of oxygen ions into the crystal structure to oxygen-deficient regions. On the contrary, H 2 during the FG annealing can efficiently infiltrate to significantly relieve the O i and V O groups in the ZnO/HfO 2 bilayer [35]. Hydrogen in FG can also significantly facilitate removing negatively charged oxygen species defects located at the grain boundaries during annealing [36]. Therefore, the FG annealing would be used for the subsequent fabrication of 3-D fin-gate ZnO Fe-FETs.  Fig. 7(b). First, a 100-nm-thick tungsten (W) layer was deposited on the SiO 2 /Si substrate. After that, the fin-shaped gate was patterned and etched using electron beam (e-beam) lithography (EBL) and SF 6 -based gas in the inductively coupled plasma-reactive ion etching (ICP-RIE) system. Then, a 12-nm HZO layer was deposited by ALD. To obtain better ferroelectricity, W was sputtered as the sacrificial layer, followed by the annealing in N 2 at 450 • C for 60 s. After etching the sacrificial layer with W etchant, which is a mixture of potassium hydroxide and potassium ferricyanide-based solution, an 8-nm ZnO channel was deposited by ALD at 150 • C. ZnO mesa was then patterned and etched. Before the deposition of source/drain electrodes, the sample was annealed in FG for 5 min. Here, the FG is still believed to be able to improve the device gate stack, as discussed in Section II. Finally, 50-nm Ti was formed by EBL, an e-beam evaporator, and a lift-off process. Fig. 7(c) shows the top-view scanning electron microscopy (SEM) image of the fabricated fin-gate ZnO Fe-FETs with several parallel fins in the channel region where the etched fin-shaped gate can be recognized. Fig. 7(d) shows the crosssectional transmission electron microscopy (TEM) images cutting along the channel width direction. The thickness of each layer could be accurately obtained. Here, the etching depth is 40 nm, and the actual fin width is about 75 nm. Good step coverage of the ZnO channel and HZO ferroelectric gate dielectric can be observed. Fig. 7(e) shows the high-angle annular-dark-field (HAADF) STEM and the corresponding energy-dispersive X-ray spectroscopy (EDX) mapping profile, indicating the uniform distribution of Zn, Hf, and Zr in each layer.

B. Characterization of W/HZO/W and W/HZO/ZnO FE Capacitors
To evaluate the ferroelectricity of the fabricated gate stack, both W/HZO/W (MFM) and W/HZO/ZnO/Ti (MFS) capacitors were examined. Fig. 8(a) and (b) shows the polarization (P) versus voltage (V ) characteristics of MFM and MFS capacitors with the voltage swept from 1 to 5 V. The ferroelectricity of these two types of capacitors can be confirmed clearly where the remanent polarization (P r ) could increase with the amplitude of the applied pulse voltage. The maximum 2P r of the MFM capacitors can achieve ∼39 µC/cm 2 . For the MFS capacitors, 2P r slightly drops to ∼30 µC/cm 2 when the sweeping voltage is 5 V, while the coercive voltage (V c ) does not experience significant change.
The reliability of the MFS capacitors was also investigated. Fig. 8(c) displays the endurance characteristics of the MFS capacitors with the applied pulse voltage ranging from ±2.5 to ±4 V, exhibiting nearly 2P r = 7.6 µC/cm 2 after being applied ±2.5 V/1 µs pulse for 10 8 cycles. The retention characteristics at room temperature of the MFS capacitors are shown in Fig. 8(d), and P r remains high after ten years as projected by extrapolating the measured results. Therefore, it is validated that the W/HZO/ZnO layers as the gate stack of the ZnO Fe-FETs have satisfactory performance. Fig. 9(a) shows the measured transfer characteristics of the planar and fin-gate ZnO Fe-FETs, where the structure of the planar Fe-FETs is similar to Fig. 2(a). The drain current of fin-gate Fe-FETs is normalized by the width of the source/drain electrodes. Both long (L ch = 1 µm) and short (L ch = 50 nm) channel Fe-FETs were measured, and they all exhibit anticlockwise hysteresis. Besides, during the dual sweeping of the transfer curves, two gate current (I g ) peaks are detected, which are attributed to the switching of the polarization of the HZO layer. Moreover, the fin-gate Fe-FETs show a comparable MW to the planar Fe-FETs, and a large  MW of ∼1.9 V could be achieved with an L ch of 1 µm. Here, V th was extracted by the constant current method at which I D is 5e − 2 µA/µm. No obvious enhancement of the ON-state current of the fin-gate ZnO Fe-FETs over the planar devices was obtained. This is because the source/drain electrodes were deposited by the e-beam evaporator and cannot completely cover the fin-shaped channel of our fin-gate ZnO Fe-FETs, leading to much higher S/D serious resistance. The SS characteristics of the planar and fin-gate Fe-FETs are shown in Fig. 9(b). An increase in SS for the scaled devices is observed, and the slightly higher SS of the fin-gate Fe-FETs may be attributed to the degradation of surface roughness and interface quality after the fin-shaped gate dry etching process. Fig. 9(c) plots the MW as a function of L ch . Despite a gradual reduction of the MW, a 1.5 VMW can still be achieved for both planar and fin-gate Fe-FETs at a scaled L ch of 50 nm, indicating the potential for ultrahigh-density applications. The difference in MW between planar and fingate Fe-FETs could come from the insufficient switching of FE polarization at the erase state. For the fin-gate Fe-FETs, when a negative voltage is applied on the gate, the electric field across  the HZO layer near the corner of the fin-shaped gate could be increased compared to the planar structure, causing more switching of the FE polarization and thus the slight higher MW. For further scaled devices with L ch close to 50 nm, the source/drain electrodes can help to switch the polarization of the FE layer in the channel region. Therefore, the MW of both planar and fin-gate ultrascaled Fe-FETs will increase and tend to merge. The reliability of the fabricated Fe-FETs is shown in Fig. 9(d) and (e). Since there are no electrodes on top of the channel region of Fe-FETs, switching the polarization of the FE layer needs different voltages. Therefore, the applied P/E conditions on Fe-FETs are not the same as that on previous capacitors. Fig. 9(d) illustrates the endurance characteristics of the ZnO Fe-FETs with an L ch of 500 nm. The MW of fin-gate Fe-FETs slightly decreases from 1.7 to 1.5 V after being applied ±4 V/10 µs pulses for 10 8 cycles, similar to the planar devices. Fig. 9(e) shows the retention characteristics of the fin-gate ZnO Fe-FETs at room temperature. The ON/OFF-state can be extrapolated to ten years without significant degradation, indicating the excellent retention characteristic of the fin-gate ZnO Fe-FETs. Fig. 10(a) and (b) plots the channel conductance changes by applying optimized programming pulses on both planar and fin-gate ZnO Fe-FETs. A drain voltage of 0.1 V is employed to read the drain current, and the insets of Fig. 10(a) and (b) introduce the pulse sequence applied on the gate terminal. Both potentiation and depression processes consist of 100 positive or negative pulses with the same pulsewidth of 1 ms and the proper pulse amplitude. As a result, the linearity of planar ZnO Fe-FETs can be extracted as 0.13 and 1.75 for the potentiation and depression process, respectively. Although the potentiation linearity of the fin-gate ZnO Fe-FETs rises to 0.63 compared to that of the planar ZnO Fe-FETs, the linearity of the depression stage gets improved to 0.12.

D. Improvement of Device Variation by 3-D Structure
The unique characteristic of the fin-gate ZnO Fe-FETs is the enlarged device active area at the same limited footprint in contrast to the planar ones. It is well known that when the active area of the Fe-FET approaches the domain size of the ferroelectric layer, a considerable device-to-device V th variation would be expected [37]. Therefore, there is a tradeoff between device density and uniformity. Fortunately, our 3-D fin-shaped architecture helps to enlarge the active area of the device, leading to better uniformity at a fixed device density or a higher device density with a fixed device uniformity than the planar devices.
To better understand this point, the device variation simulation was carried out by Monte Carlo methods, as illustrated in Fig. 11(a). A multidomain time-dependent Landau-Ginzburg (TDLG)-based model was applied in the simulation [38], which was first calibrated with the measured P-V characteristics [see Fig. 11(b)]. From the fitting result, a normal distribution of E c can be obtained with the mean value (µ) and standard deviation (σ ) of 1.12 and 0.22 MV/cm, respectively [see Fig. 11(c)]. Here, the domain size of the ferroelectric layer is assumed to be 100 nm 2 . To extract the V th variation of Fe-FETs, we first assume the planar device with L ch and channel width (W ch ) of 20 and 50 nm. Then, the active area of the device and the corresponding number of domains can be calculated. For the fin-gate Fe-FETs, considering the onefin structure, L ch and the fin width (W fin ) were set as L ch and W ch of the planar device. The fin height (H fin ) varied from 50 to 250 nm. Therefore, the difference in the active area between planar and fin-gate Fe-FETs at the fixed device footprint can be obtained. The variation data of each device dimension is summarized from 50 devices simulated by our Fe-FET model with multidomain dynamic switching characteristics [38], where domain parameters are randomly generated according to Fig. 11(c). Fig. 11(d) shows the simulated V th distribution of planar and fin-gate Fe-FETs with H fin of 50, 100, and 500 nm. Here, the V th margin represents the gap between two V th states. The larger device area could result in a more uniform distribution of V th . Fig. 11(e) outlines the relationship between the V th margin and the aspect ratio, which is defined as the ratio of H fin over W fin . The V th margin and aspect ratio can be roughly fit by a hyperbola relation (red dashed line). The orange dashed line represents the V th margin of planar devices. Compared to the planar Fe-FETs, a significant improvement of the V th margin for the fin-gate Fe-FETs can be observed, and the fin-shaped gate with a higher aspect ratio could further enhance the V th margin. Therefore, the 3-D fin-gate Fe-FETs could be seen as a promising solution for ultrascaled memory circuits. Table II benchmarks the OS-based Fe-FETs with HZO as the ferroelectric material. This work is one of the very few reports on 3-D OS Fe-FETs. Among all the reported Fe-FETs, our 3-D devices using the ALD-deposited ZnO channel achieved performance on par with those of best planar devices, including both ALD and sputter-deposited OS.

IV. CONCLUSION
In summary, we demonstrate the BEOL-compatible 3-D fingate Fe-FETs enabled by an ALD-deposited ZnO channel. Extensive materials analysis and electrical characterizations were carried out to optimize the ALD process of the ZnO film and the gate stack. Our fin-gate ZnO Fe-FETs show comparable key electrical performance indicators, that is, MW, endurance, and retention, to the planar ones, while the deviceto-device variation can be considerably improved based on the 3-D fin structure. This work demonstrates the great potential of our devices in ultrahigh-density storage and in-memory computing applications.