IGBT Reverse Transfer Dynamic Capacitance

Small-signal capacitance in every datasheet of insulated gate bipolar transistor (IGBT) is not accurate for understanding IGBT’s switching because the bipolar current in the device creates abnormal depletion profiles. IGBT’s reverse transfer dynamic capacitance is extracted for the first time with a five-contact method. While small-signal capacitance does not allow any current flow in the drift region due to the ground gate, the dynamic capacitance is the output of the time-dependent bipolar carriers during the inductive switching. For this reason, the magnitude and the shape of the dynamic capacitance are quite different from the small-signal capacitance found in most of the commercial datasheet. The discrepancy between the dynamic <inline-formula> <tex-math notation="LaTeX">${C}_{\text {GC}}$ </tex-math></inline-formula> and the small-signal <inline-formula> <tex-math notation="LaTeX">${C}_{\text {GC}}$ </tex-math></inline-formula> raises a fundamental question of whether the small-signal <inline-formula> <tex-math notation="LaTeX">${C}_{\text {GC}}$ </tex-math></inline-formula> in the datasheet is useful for considering the device’s dynamic performance.


IGBT Reverse Transfer Dynamic Capacitance H. Kang
Abstract -Small-signal capacitance in every datasheet of insulated gate bipolar transistor (IGBT) is not accurate for understanding IGBT's switching because the bipolar current in the device creates abnormal depletion profiles. IGBT's reverse transfer dynamic capacitance is extracted for the first time with a five-contact method. While small-signal capacitance does not allow any current flow in the drift region due to the ground gate, the dynamic capacitance is the output of the time-dependent bipolar carriers during the inductive switching. For this reason, the magnitude and the shape of the dynamic capacitance are quite different from the small-signal capacitance found in most of the commercial datasheet. The discrepancy between the dynamic C GC and the small-signal C GC raises a fundamental question of whether the small-signal C GC in the datasheet is useful for considering the device's dynamic performance.

I. INTRODUCTION
I NSULATED gate bipolar transistors (IGBTs) have been one of the most popular devices in high-voltage power industries due to their high current capability and cheap fabrication cost [1], [2], [3], [4]. In an effort to optimize the ON-state conduction loss and the turn-off switching loss, several types of novel IGBT structures have been suggested [5], [6], [7], [8]. Since IGBTs' conducting and switching behaviors are based on bipolar (hole-electron) carrier movement, to interpret the devices' operating characteristics, a wide range of analytic modeling has been performed [9], [10], [11], [12], [13], [14], [15], [16]. Although those models were applied to very limited structures, indeed, they improved the understanding of the detailed bipolar conducting mechanism in IGBTs. In the transient modeling or the simulation of IGBTs, the small-signal reverse transfer capacitance C rss (or gateto-collector capacitance) has been the main parameter for determining switching delay and speed. However, one fundamental question has not been resolved yet: is the small-signal capacitance enough for forecasting the dynamic switching performance? Small-signal measurement is carried out when the device is in OFF-state. The gate is shorted with the emitter and they are grounded. Only the collector voltage increases continuously by applying a small ac perturbation. The measured small-signal capacitance is the same as the series combination of the oxide capacitance and the depletion capacitance. The small-signal measurement, therefore, does not allow a current flow in the drift region (conductivity modulation) simply presenting the p-n junction depletion capacitance. Most of the commercial IGBT datasheets contain the small-signal reverse transfer capacitance.
However, since the injected bipolar carriers overwhelm the doping concentration of IGBTs' drift region during the turning-on and turning-off transitions, the bipolar carriers will significantly affect the depletion profiles in the drift region as well as the switching speed. More specifically, the electrons and the holes near the depletion boundary will be rapidly swept to each contact under the saturation velocities. The carriers moving across the depletion region modulates the ion concentration in the drift region depending on the saturation velocity and the current density given by the following equations [17], [18]: where N D , n, and p are the doping concentration in the drift region, the electron density, and the hole density in the depletion region, respectively. J n , J p , V sat,n , and V sat, p are the electron current density, hole current density, electron saturation velocity, and hole saturation velocity in the depletion region, respectively. E, q, and ε S are the electric field in the depletion region, unit charge, and the permittivity of semiconductors, respectively. In other words, the drift region's charge concentration is not fixed at the doping concentration (N D ) and the depletion profiles during the dynamic switching will be way different from the small-signal measurement. During the small-signal measurement, the IGBT device is not turned on (without gate bias and current in the channel and the drift region), and only a small ac perturbation is applied to the collector terminal at a specific dc voltage. Therefore, the dynamic capacitance, which is reflected by the depletion profiles in the drift region during the switching transient, will be quite different from that of the small signal. This means that the dynamic switching (turning on and turning off) behavior is not the output of the smallsignal capacitance, but the dynamic capacitance. However, every datasheet of IGBTs has been still adopting small-signal capacitance so far and the values in the datasheets are not practically useful.
Another problem of understanding IGBTs' dynamic switching is in power electronics perspective approach with three terminals. More specifically, although power electronics have been adopting a simple device capacitance model as shown in Fig. 1(a), there is no way to conjecture the abnormal current path but exist in reality, as shown in Fig. 1(b). As it will be discussed in the main section, during the turn-off transient, a part of the collector current sequentially flows across the IGBT's channel, the gate-to-emitter (C GE ), gate-tocollector (C GC ), and collector-to-emitter (C CE ) capacitances. This complicated current flow is nearly impossible to be detected in conventional measurement methods.
This study, for the first time, investigates the reverse transfer capacitance during the dynamic switching with a state-of-theart field stop IGBT structure. For this, we applied five terminals to contact the IGBT to specify the gate-to-emitter current (I GE ), the gate-to-collector current (I GC ), the channel current (I n+ ), the hole current (I p+ ), and the collector current (I C ), as shown in Fig. 2. The GE and GC contacts for I GE and I GC are split by 1.0-nm gap at the boundary between the p-body region (p-well) and the n-charge storage region (nCS) [see the inset of Fig. 2(a)]. Since the n-CS (charge storage) region is connected to the drain side, the boundary between the GE and the GC contacts must be the interface between the p-well and the n-CS. The five-contact method will be able to provide a detailed switching mechanism, negative capacitance during the turn-on, and a deeper understanding than the conventional three contacts [19], [20], [21]. Specifically, the gate contact consists of the gate-to-emitter contact, GE, and the gate-to-collector contact, GC.
During the turn-on transient, the gate-to-emitter displacement current, I GE , will flow into the GE to control the channel of the MOS and the gate-to-collector displacement current, I GC , will flow into the GC to control the gate-to-collector voltage. From the collector voltage transition and I GC on the time domain, the dynamic gate-to-collector capacitance, C GC.Dynamic , can be extracted where V GE , V CE , and V GC are the gate-to-emitter voltage, the collector-to-emitter voltage, and the gate-to-collector voltage, respectively. The emitter contact (on the top of the device) consists of the n+ contact and the p+ contact. The MOS channel current will flow through the n+ contact (electron current only) and the hole current from the drift region will flow through the p+ contact (hole current only). From this five-contact method, the behavior of forward recovery during the turn-on and the negative capacitance during both the turn-on and the turn-off switching can be simply detected.

II. DEVICE DESIGN AND SIMULATION SETTINGS
The field stop IGBT's structure and the thermal process in the simulation are based on the practical device design and the process conditions, which are under development in Magnachip for the next generation with 650-V rating. The cell pitch of the IGBT is 1.5 μm, and the mesa width and the trench width for the trench gate channel are 0.9 and 0.6 μm, respectively. The depth of the trench is 4.8 μm. The thickness of the drift region, including buffer layer, is 55 μm. The charge storage (CS) layer is located under the p-body region and the p-collector region is formed by shallow boron ion implantation and laser annealing. The obtained breakdown voltage is 725 V. The applied trench configuration in this simulation is targeting full channel trench gate IGBTs without dummy emitter trench [22], [23], which are normally applicable to the resonant converters. The full channel gate structure features the lowest ON-state voltage drop (the highest saturation current) and the lowest short-circuit capability (poor dynamic ruggedness). Since all the trenches of the IGBT are connected to the gate terminal, the input capacitance (C iss ) and the reverse transfer capacitance (C rss ) will be the highest showing the slowest switching speed. As the ratio of the emitter trench increases (emitter replaces with the gate), the channel density of the IGBT decreases and the ON-state voltage increases due to the lowered electron injection from the channel. The lowered channel density (increased emitter trench ratio to the gate trench) leads to a lowered saturation current level and increased short-circuit capability (improved dynamic ruggedness). In practical applications, IGBT can be customized from the full channel to very low channel density, for example, 1(gate trench):19(emitter trench), depending on customers' short-circuit requirements.
For inductive switching, device-circuit mixed-mode simulation is employed in sentaurus workbench (SWB) provided by Synopsis Inc. The applied V CC is 400 V and the gate voltage is 15 V. During the turn-on, the diode's reverse recovery characteristics contribute to the peak current of the IGBT at the initial stage of Miller plateau and the dV /dt during the Miller plateau. More specifically, the peak current and dV /dt are highly dependent on the IGBT's input capacitance and the diode's reverse recovery softness. To investigate the device's pure dynamic capacitance, an ideal diode (without reverse recovery) is used on the inductive load. The external gate resistance, R G , is 10 and the stray inductance at each terminal is ignored. The operating temperature is 300 K. As the data are not shown here, we confirmed that the operating behaviors show very similar waveforms and the dynamic capacitance even under high temperatures up to 450 K. The physical models in the simulation include Shockley-Read-Hall recombination, Auger recombination, doping-dependent mobility, electric field-dependent mobility, field-effect mobility, carrierto-carrier scattering, carrier velocity saturation, and impact ionization models. With the electric field-dependent mobility and velocity saturation model, the electric field distortion by high density of holes and electrons in the depletion region during the switching phase can be observed.

III. TURN-ON SWITCHING
For turning on the IGBT, as shown in Fig. 2, the gate current, I G , and the collector current, I C , flow out through the emitter, I E Fig. 3 shows the voltage and the current waveforms during the inductive turn-on switching.
t 0 -t 1 : As soon as the external gate bias (15 V) is applied, the gate current (I G ) flows into the GE (I GE ) and GC (I GC ) terminals charging the input capacitance. The gate voltage reaches its threshold voltage, V TH . t 1 -t 2 : Once the gate channel is formed at t 1 (the threshold voltage), the channel current (I n+ ) increases rapidly showing the following relationship with the gate voltage: where g m is the transconductance of the MOS channel. One important finding is that the hole current (I p+ ) also increases quickly after the IGBT's threshold voltage. It has been believed that heretofore, the hole current just after V TH is nearly zero or very small because of the forward recovery process [15], i.e., time is not enough for the drift region to be modulated by hole carriers. Despite the low hole carrier concentration, the injected holes from the collector are able to be swept rapidly across the drift region because the drift region is fully depleted by V CC . In other words, the small amount of hole carriers with the saturation velocity presents a quite high hole current. t 2 -t 3 : When the sum of the channel current (I n+ ) and the hole current (I p+ ) reaches its driving current level (30 A), the Miller plateau phase is started. Right after t 2 , the gate-toemitter displacement current (I GE ) drops to a slightly negative value (−0.1 A) by decreasing the channel current (I n+ ). This is because of the negative capacitance in which excessive holes below the gate oxide push out the positive charges on the gate terminal by slightly lowering the gate potential as well as accumulated electrons on the channel. Therefore, the degree of the negative capacitance can be simply detected by the amount of the negative shooting of the gate-to-emitter current.
It should be noted that the slight fluctuation of I p+ is due to the negative capacitance around the gate [6], [24], [25], [26]. As an accumulation (electrons) layer is formed below the gate oxide (bottom of the trench gate), the injected holes from the collector can be easily attracted by the electrons on the accumulation layers with the help of the high V CE . The attracted holes, in turn, lead to a slight surge in hole current (I p+ ) and hole displacement current (I GC , from the accumulation layer to the GC terminal). The hole displacement current across the GC terminal lowers the level of I GC . The negative capacitance effect is finally mitigated by the lowered V CE . The detailed current flow in the gate terminals during the negative capacitance is observed for the first time. t 3 -t 4 : At t 3 , the depletion region under the trench gate is transformed to an accumulation region and the gate-tocollector capacitance becomes large because the depletion capacitance in the drift region is removed. The increased gateto-collector capacitance creates a very slow dV CE /dt slope. The MOS channel is in the saturation region and both I GC and I GE are used to remove the pinchoff region at the end of the MOS channel.
After t 4 : The plateau phase is ended when the MOS channel's operation changes to the linear region from the saturation. The gate voltage keeps increasing with the continuous inflow of I GE and I GC . The steady increase of the hole current (I p+ ) is the indication that the forward recovery in the drift  Fig. 4 shows a schematic circuit configuration for the IGBT's turn-off switching. During the turn-off transition, as shown in Fig. 4. a part of the collector current flows out across the gate as a displacement current and the rest flows out to the emitter having the following relationship:

IV. TURN-OFF SWITCHING
Fig . 5 shows the simulated waveforms during the turn-off inductive switching. t 0 -t 1 : As soon as the external gate bias becomes zero at t 0 , both I GE and I GC flow out from the GE and GC, respectively. The outflow of the gate displacement current lasts until the gate potential reaches the plateau voltage. t 1 -t 2 : At t 1 , due to the decrease in the gate potential, the MOS channel's operation region changes to the saturation from the linear. Both the discharging currents, I GE and I GC , form a larger depletion region at the end of the channel (pinchoff) by pushing the MOS channel to a deeper saturation region. This phase lasts until the accumulation region under the gate disappears. t 2 -t 3 : At t 2 , the accumulation region under the gate starts to be depleted by the continuous outflowing I GC . The gateto-collector capacitance (C GC ) becomes relatively small by the series depletion capacitance under the gate and the small C GC leads to a rapid increase in V CE . Due to the increase of V CE (the expansion of the depletion region across the drift region), the hole current (I p+ ) increases rapidly because the holes in the drift region can be swept quickly across the depletion region. By the amount of the increased hole current, the channel current (I n+ ) decreases, and the channel finally turned off at t 3 . Meanwhile, the gate voltage also decreases by the amount of the channel current given by (6).  It should be noted that, in the case of the MOSFETs, V CE will be V CC at t 2 (the end of the plateau phase). For IGBTs, however, due to the remained holes in the drift region, the rise of V CE is delayed until the channel current becomes zero (when V GE arrives at V TH ).
A new finding in this phase is that there is a sudden discharging and charging current between GE and GC terminals. The gate potential keeps decreasing, but the GE terminal is rather charged. The abnormal phenomenon is caused by a rapid decrease in the hole current density (I P+ ) under the gate oxide. A portion of the outflowing gate-to-emitter current (I GE ) diverts to the gate-to-collector current (I GC ), as shown in Fig. 6. This can be explained by the weakened negative capacitance effect. Negative capacitance is the increased potential under the gate oxide caused by hole carriers with a high electric field [24], [25]. As the hole current density decreases, the potential of the gate adjacent to the top drift region becomes small creating a displacement current. This effect (the decreased hole density under the gate oxide) is seen as if the gate-to-collector capacitance is charged again. It is noteworthy that the current path in the device shown in Fig. 6 is hardly depicted in the power electronics model. More specifically, in the power electronics model, I GE cannot flow into C GC due to the higher collector potential than the emitter. This is an advantageous example of the mixed-mode simulation over the explanation of the conventional power electronics model. Fig. 7 shows the dynamic C GC and the hysteresis with respect to the V CE for the turn-on and the turn-off transitions. The dynamic C GC was extracted by using I GC , V CE , and  V GE waveforms shown in Figs. 3 and 5, and (4). The smallsignal C GC simulated at 100 kHz is inserted for comparison. In the case of the small-signal mode, there is no channel and accumulation layer between the semiconductor and the gate oxide because the gate terminal is grounded. Indeed, the slightly depleted interface by the n+ poly gate presents a relatively low C rss value compared to the dynamic C GC .

V. DYNAMIC CAPACITANCE AND HYSTERESIS
Phase A-B: Both the turn-on (after Miller phase) and the turn-off (before Miller phase) transitions are in the high-level injection having an accumulation layer under the gate. It is noteworthy that the dynamic C GC of the turn-on continuously increases as V CE decreases. There is a capacitance (depletion region) between the p-body (or p-well) and the CS regions. The oxide capacitance adjacent to the CS region will form a series capacitance with the capacitance (C GCS -C ECS ), as shown in Fig. 8. For example, in the initial stage of the accumulation region being formed (during the turn-on), the depletion region between the p-body and the CS region is wide having a small C ECS . As the forward recovery progresses, the depletion width for the C ECS will become narrow. This is why C GC continuously grows as the turning-on device passes the phase from B to A. The same mechanism will be applied to planar gate IGBTs as well.
Phase B-C: Around V CE = 9-27 V, both the turn-on and the turn-off switching are in the Miller plateau and the turn-on dynamic C GC is abnormally higher than the turn-off. The reason can be explained by V CE when the depletion (accumulation) layer under the gate changes to the accumulation (depletion) layer, as shown in Fig. 9. In the case of turn-off, the accumulation layer under the gate starts to be depleted around V CE = 9 V. Since the high hole density is remained in the drift region, the potential across the drift region is very small. In the case of the turn-on, however, the hole density in the drift region is relatively small because the IGBT is in an initial state of forward recovery. Therefore, when the depletion layer under the gate changes to the accumulation layer, a large portion of V CE is sustained across the drift region, i.e., the accumulation layer appears around 27 V for the turn-on and the accumulation disappears around 9 V for the turn-off.
From the extraction of the dynamic transfer capacitance (C GC ) shown in Fig. 9, one would be able to relate the dynamic C GC with Q G in a commercial datasheet. Since the time between t 2 and t 4 in Fig. 3 is normally known as the transfer period, the gate current should flow only through the collector-to-gate capacitance. If this (I G = I GC during t 2 -t 4 ) is true, it is possible to obtain the dynamic capacitance from Q G measurement. However, the ideal situation never happens even in MOSFETs because some portion of the gate current generally flows into the gate-to-source capacitance to remove the pinchoff (depletion) region in the MOS channel [27].

VI. CONCLUSION
IGBT's reverse transfer dynamic capacitance was analyzed for the first time. For this purpose, IGBT's contact was arranged five terminals to measure the channel current, hole current, gate-to-emitter current, and the gate-to-collector current. The inductive switching waveforms with five contacts provided a deeper insight into the detailed current flow mechanism in the device, especially for the dynamic hole current fluctuation and the negative capacitance. For example, the misunderstanding of the hole current behavior during the turnon and the turn-off is corrected. The misbelief has originated from the absence of the hole current extraction and the limited current path configuration in the power electronics model. From V CE , V GE , and I GC , the dynamic C GC during the switching was extracted. The magnitude and the shape of the dynamic C GC were quite different from the small-signal C GC because of the hole carrier movement in the drift region. The turn-on and the turn-off dynamic C GC show asymmetric capacitance curves due to the forward recovery process of the IGBT.