Extended Scale Length Theory for Low-Dimensional Field-Effect Transistors

Low-dimensional (low-D) semiconductors such as carbon nanotubes (CNTs) and 2-D materials are promising channel materials for nanoscale field-effect transistors (FETs) due to their superior electrostatic control. However, classical scale length theory (SLT) does not incorporate the effect of channel extensions, which becomes crucial for thin channels (< 10 nm) and short gate lengths. Here, we extend the classical SLT by introducing two boundary coupling parameters, which describe the impact of gate and drain biases on the source- and drain-channel junction potentials. Moreover, we introduce a general expression for the scale length specifically for low-D FETs. This extended SLT accurately describes electrostatic short-channel effects (SCEs) of low-D FETs, with < 5% error in subthreshold slope over a wide range of parameters versus > $2\times $ error using the classical SLT. The extended SLT is based on three parameters (scale length, gate, and drain boundary coupling parameters) which can be extracted from potential profiles or FET transfer characteristics. In addition, the extended SLT uses analytical closed-form expressions that can be easily included in a compact model to facilitate design-technology co-optimization (DTCO) with low-D FETs to leverage the crucial role of their extensions.


I. INTRODUCTION
T HE classical scale length theory (SLT) [1]- [5] has facilitated the design of bulk 3-D semiconductor field-effect transistors (FETs) by introducing a single electrostatic scale length, , which quantifies the distance that lateral electric fields penetrate into the FET channel [1]. Short-channel effects (SCEs), including drain-induced barrier lowering (DIBL), threshold voltage (V t ) roll-off, and subthreshold swing (SS) degradation, can be predicted for arbitrary gate lengths (L g ) using simple analytical expressions with L g and as the only parameters. Due to its accuracy and simplicity, the classical SLT has become ubiquitous in a device engineer's toolkit [4].
However, unlike their bulk 3-D counterparts, low-D FETs have depletion lengths in their extension regions that are comparable with [14]- [16] due to the low dimensionality, as shown in Fig. 1(a). Consequently, the extension regions of low-D FETs partially sustain the potential drop between the channel and the source or drain, thereby improving the electrostatic control and reducing SCEs [6], [17]- [19]. However, classical SLT developed for bulk 3-D-semiconductor channels [1], [3] neglects this potential drop and, therefore, overestimates SCEs for low-D FETs. This limitation of the classical SLT precludes device engineers from realizing potential miniaturization opportunities and associated design and optimization of low-D FETs [see Fig. 1(b) and (c)]. For instance, a reduction of the extensions doping [17], [19] and the engineering of the spacer dielectric surrounding the source/drain extensions [20] lead only to a small improvement in the SCEs for bulk 3-D-semiconductors. However, the same techniques have a greater impact on low-D FETs SCEs, due  L g /Λ ratio required to achieve SS = 80 mV/dec versus channel thickness. This ratio was extracted with Sentaurus for a 2-D DG FET with t ox = 2 nm (black circles) and t ox = 10 nm (blue circles), extension doping = 10 20 cm −3 , and ox = spa = 20. The red dashed line shows the ratio of L g /Λ required to achieve the same SS according to classical SLT. (b) Transfer characteristics of 2-D DG FETs simulated with Sentaurus for t ch = 1 and 100 nm, t ox = 3 nm, and other parameters as in (a). For each case, L g is chosen to have the same L g /Λ ratio. Red line indicates the slope predicted by classical SLT.
to their reduced dimensionality, and thus represent additional knobs to improve the performance of low-D FETs.
As an example of SCE overestimation, we plot the value of L g / required to obtain SS = 80 mV/dec in a 2-D double-gate (DG) FET, as predicted by Sentaurus [21], at various channel thicknesses (t ch ) in Fig. 2(a). While the classical SLT predicts that L g / ≈ 1.3 should yield an SS = 80 mV/dec regardless of t ch (red dashed line), we observe that much smaller values of L g / yield this SS as t ch decreases below 10 nm. The subthreshold current of small-t ch FETs (i.e., <10 nm) is likewise overestimated by classical SLT, as shown in Fig. 2 This work is an extension of previous SLTs targeting low-D FETs (e.g., 2-D FETs [22], CNFETs [23]), because it simultaneously includes the impact of channel geometry, extension doping [18], [19], [24] and of the spacer dielectric constant [20], [25]. In our previous work [6], we introduced the boundary coupling parameters G and D and applied the theory to CNFETs. In contrast, here, we: 1) demonstrate that the extended SLT also works for 2-D FETs; 2) introduce a general expression for in low-D FETs; and 3) introduce a new procedure to derive the boundary coupling parameters from potential profiles (similar to the conventional procedure used to extract the scale length [22]) and from FET transfer characteristics.
The extended SLT abstracts the complexity of the specific device architecture to three physics-based parameters that uniquely determine electrostatic control and SCEs. Moreover, because the extended SLT is based on closed-form expressions, it is easily incorporated into compact models. The design space of low-D FETs, including both material selection and device architecture, makes such compact models crucial for enabling extensive design-technology co-optimization (DTCO) of emerging low-D FETs and projecting their benefits [6].
In Section II, after introducing the extended SLT and justifying the physical meaning of new coupling parameters, we describe a procedure to extract the extended SLT parameters, showing that the extended theory can accurately predict SCEs in low-D FETs. In Section III, we apply the extended SLT to 1-D and 2-D FETs and show the dependence of electrostatic control on device geometry, dimensionality, and technology parameters (such as extension doping and dielectric constants). Given their superior electrostatic control [6], [26]- [28], in this work, we consider three FET geometries: 1-D gate-all-around (GAA), 1-D DG-FETs, and 2-D DG-FETs [see Fig. 1(c)]. Finally, we conclude in Section IV with an outlook of how these findings will influence future designs of low-D FETs. Because the focus of this work is electrostatic control of the FET, we do not include the impact of direct source-drain tunneling [29] and band-toband tunneling [30], [31]. However, we note that the extended SLT is representative of the analytical framework necessary to model band profiles, including the modeling of tunneling currents, as previously shown in [6]. As an additional example, the extended SLT can potentially be used in compact models for tunnel FETs [32] based on low-D materials, where the knowledge of the potential profile near the junction is crucial for the derivation of the tunneling currents. Fig. 1(b) shows the schematic of device structures considered in this work. Source and drain terminals are separated from the intrinsic channel by doped extensions with a steplike profile so that the gate electrode is aligned with the edge of the extension regions (i.e., the gate length L g and channel length L ch coincide). In this section, we focus on 2-D DG to derive the extended SLT formalism. However, the extended SLT parameters are derived in an identical fashion for other geometries (see Section III).

II. EXTENDED SLT A. Formalism
In classical SLT, the potential profile along the channel is expressed as [33] where V gs is the gate-to-source voltage, and n are different orders of the electrostatic scale length. For the sake of simplicity, compared with [33, eq. 1], we consider y = 0 at the center of the channel. The coefficients b n and c n satisfy the boundary conditions at the junctions between the channel and the extensions. In classical SLT [1], [3], [5], b n and c n are derived by imposing a constant potential in the doped extensions, equal to bi and bi + V ds for the source-and drain-side extensions, respectively, where bi is the built-in potential [5] and V ds is the drain-to-source bias. In low-D FETs, where the vanishing thickness of the channel makes the potential drop along y-direction negligible, (1) can be further simplified as [33] ( While the assumption of constant potential in the extensions is appropriate for bulk 3-D-semiconductors FETs, low-D FETs are characterized by relatively large depletion lengths in their source and drain extensions, violating this assumption [see Fig. 1(a)] and, in turn, rendering classical SLT inappropriate for low-D FETs with doped extensions. Here, we aim to extend the classical SLT to low-D FETs by deriving an equation similar to (2) without imposing constant potentials throughout the source-and drain-side extensions.
To discern the role of extensions, we begin by modeling the potential near the junction as a piecewise function, similar to the derivation of [17] and [18]. Considering the potential at the source junction (i.e., x = 0) and for L g , (2) can be simplified by noting that Therefore We express the potential on the source side of the junction as is a generic function that describes the potential drop in the extension. While general expressions for g(x) can Piecewise function used to model the potential near the junction between channel and extension and definitions of key modeling parameters used to derive the extended SLT.
be complex [15], [34], a simple model for SCEs can be derived from the following equation, which is valid at x = 0: where represents an effective depletion length, defined as the intercept between the prolongation of the derivative in x = 0 and (x) = bi (see Fig. 3). In principle, in (9) is a function of V gs , V ds , and bi . However, for the sake of simplicity, we keep only the 0 th order and consider two fixed values for the source and drain extensions ( s and d , respectively). As we will demonstrate shortly, this approximation sufficiently captures the electrostatic behavior of low-D FETs.
The assumption of constant is furthermore justified by noting that the charge in the depletion tails of low-D junctions has a negligible impact on the potential and electric field near the junction [34]. Next, we impose continuity of the electrostatic potential and electric field at the source junction (see Fig. 3) Equations (9)-(11) can be solved to find which shows how the total potential difference V gs + bi is partitioned between the extension and the channel. The above derivation can be repeated at the drain side to arrive at a similar expression for the drain junction potential Equations (12) and (13) represent a more generalized form of the boundary conditions used in classical SLT. If s and d , then j,s = bi and j,d = bi +V ds , restoring the classical SLT assumption. However, if ∼ s or d (as is the case of low-D FETs [15], [16]), this simple model captures the effect of the finite depletion length, thus extending classical SLT to low-D FETs.
The boundary coupling parameters introduced in [6], which describe how j,s and j,d respond to the applied gate and drain voltages, can be derived from (12) and (13) as With these definitions, we express the potential profile in the gate region as Given the definitions in (14) and (15), G ∼ D ∼ 1 for bulk 3-D-semiconductor FETs ( ) and (16) becomes identical to the classical expression (2)-(4). However, in the general case, G and D are in the range of 0-1, incorporating the finite depletion length into the theory. Here, we note that the definition of in the extended SLT is unchanged from that of classical SLT. However, we emphasize that cannot univocally describe the electrostatics of low-D FETs because two low-D FETs might have equal and different SCEs. These new parameters are thus crucial for predicting SCEs in low-D FETs.

B. Extended SLT Parameters Extraction Procedure
The extended SLT parameters (, G , and D ) can be extracted from potential profiles along the channel at different gate lengths and bias conditions (see Fig. 4). After simulating surface potential profiles for a device architecture of interest at various gate lengths [see Fig. 4(a)], we calculate by plotting the change in the minimum of the potential as a function of L g (as in [22]). For a small V ds , the potential minimum is approximately at the center of the channel. Therefore In the limit L g Thus, can be extracted from the slope of the linear fit of (18), as shown in Fig. 4(b). As G and D both appear in the intercept of (18), these parameters are likewise extracted by plotting f [defined in (19)] as functions of V gs (with V ds = 0) and V ds (with V gs = 0), respectively, and finding the slopes of the linear fits, as shown in Fig. 4(c) and (d) (note the factor 1/2 in the derivation of G ). Here, we note that the linearity of the relation between f and the applied bias confirms that the 0 th order of sufficiently captures the electrostatic behavior of low-D FETs. Finally, even though not necessary to derive SCEs, the effective value of bi is found in a similar way from the limit of f for V gs that tends to zero (assuming V ds = 0). An approximation of the extended SLT parameters can be derived from FET I d -V gs transfer characteristics. A rigorous expression for the leakage current as a function of potential profile can be complex and involves numerical integrals. This is because, as noted in [33], the current continuity equation leads to a shift in the electron quasi Fermi level along the channel, making an analytical solution difficult to attain. As a result, the potential profile minimum min , relative to the Fermi level in the source, overestimates the actual potential barrier. However, approximate values for extended SLT parameters can still be analytically derived by considering an effective barrier height eff . Considering diffusive transport, the leakage current is where is a prefactor independent of L g and biasing conditions. In case of quasi-ballistic transport, (20) should be adapted considering L g -dependent apparent mobility [35]. For qV ds k B T , (20) leads to where I ref is the long-channel drain current at specific V gs and V ds [see Fig. 4(e)], L ref is the reference long-channel length, and eff is the change of the effective potential barrier between the long-channel device and the device with L g . The extended SLT parameters can then be derived following the procedure outlined in Fig. 4(b)-(d). Fig. 4(f) shows that, despite the introduction of an effective barrier height, the extended SLT parameters are in good agreement with those extracted from the potential profiles, with discrepancies in , G , and D < 8% using parameters in Fig. 4. Fig. 5(a) shows good agreement between the model and the profile simulated with Sentaurus for a 2-D DG FET, accurately reproducing the potential near the boundary conditions (i.e., the junction potentials) and at the minimum of the barrier. In this section, we leverage the extended SLT to analytically derive equations to predict SCEs in low-D FETs.

C. Short-Channel Effects
The SS quantifies the control of the gate over the channel. Without considering the impact of interface traps (which can be added subsequently), SS approaches ∼60 mV/dec for a long-channel device (i.e., L g ) due to the small body thickness in low-D FETs [33]. As the gate length is reduced, the impact of source and drain fringe fields decreases the coupling between the gate and the channel, leading to an increase in SS. Assuming L g and in the limit of small V ds , we derive SS from (11) as The reduction of the potential barrier as a function of V ds is known as DIBL. Under the same assumptions Therefore, unlike bulk 3D-semiconductor FETs, whose SS and DIBL depend only on L g /, the SS and DIBL of low-D FETs are influenced by finite depletion lengths and hence also depend on G and D . On the contrary, we note that the V t roll-off is invariant to G and D since the junction potentials are constant as L g is reduced and, hence, the coupling parameters do not affect the roll-off. Accordingly, V t roll-off of low-D FETs can still be described solely based on the L g / ratio [see Fig. 5(d)], just as is the case with bulk 3-D-semiconductors FETs. Therefore, low-D FETs can simultaneously show significant V t roll-offs and yet have small DIBL (if D ∼ 0) or small SS deterioration (if G ∼ 0), unlike bulk 3-D-semiconductors FETs, whose SS, DIBL, and V t rolloffs are all inherently coupled.

III. FET DESIGN IMPACT ON EXTENDED SLT PARAMETERS
Next, we apply the extended SLT to low-D FET geometries including 1-D GAA FETs, 1-D DG FETs, and 2-D DG FETs [cross sections in Fig. 1(c)]. We extract the extended SLT parameters from potential profiles simulated using both Sentaurus and Non-Equilibrium Green's Function (NEGF) simulators and compare SCEs predicted by the model to simulated SCEs. While NEGF intrinsically considers quantum effects, we do not include quantum corrections in Sentaurus. However, as demonstrated shortly, the extended theory accurately reproduces SCEs predicted from both Sentaurus and NEGF, suggesting that scale length and boundary coupling coefficients are dictated mainly by electrostatics.
When simulating with Sentaurus, we use generic materials with parameters in Table I. When simulating with NEGF, we use CNTs for 1-D FETs [36], and monolayer black phosphorous (BP) and monolayer HfS 2 for 2-D FETs (using in-house code [20], [37]). We consider equal t ch and ch for 2-D FETs (see Table I) to highlight the role of the different density of states (DOS). Although extended SLT can be applied to single gate (SG) FETs [6] by introducing   Table I.
an L g -dependent [38], we leave this application to future studies.

A. Scale Length
We extract for three geometries [see Fig. 1(c)] with different combinations of t ch , t ox , ox , and spa across all combinations of variables shown in Table I (see Fig. 6).
A general expression for in low-D FETs is where A is a geometry-dependent coefficient and is a corrective factor that accounts for the different cross-sectional areas (normal to the source-to-drain direction) of planar (i.e., 2-D) and cylindrical (i.e., 1-D) channels  (25) where Area ch and Area ox are the cross-sectional areas (normal to the source-to-drain direction) of channel and gate oxide, respectively. Empirically, we find that for 1-D GAA, 1-D DG, and 2-D DG FETs, A = 4.81 (in agreement with [23]), 3.23, and 3.13 (close to the value proposed in [22]). We note that a higher A implies a smaller and thus a stronger electrostatic control.
Critically, the concept of equivalent oxide thickness (EOT) is not applicable to low-D FETs, as depends primarily on the physical thickness of the gate oxide t ox , while the dielectric constants play only a minor role (also noted in [22]). This arises from the vanishing channel thickness; because only a small part of the source and drain fringe fields passes through the channel, the ratio between channel and oxide dielectric constants has minimal impact. The dielectric constant ratio is even less important in 1-D FETs, since the cross-sectional area of the channel is a smaller part of the total area due to the cylindrical channel geometry [see Fig. 1(c)]. As mentioned earlier, this effect is captured by . For 1-D GAA and DG, is given by, respectively, (26) where the width of 1-D DG is t ch + 2t ox [see Fig. 1(c)]. In this case, if tends to zero (as in 1-D with t ox t ch ), the dielectric constant ratio can be ignored altogether.

B. Boundary Coupling Parameters
Low-D FETs exhibit numerous tradeoffs between device geometry, extension doping, and dielectric constants. These tradeoffs are not present in bulk 3-D-semiconductor FETs and are likewise not captured by [6]. We show that extended SLT and the new boundary coupling coefficients capture these effects (see Fig. 7) and, therefore, play a crucial role in the DTCO of low-D FETs (e.g., [6]).
We begin by considering G and D as functions of the extension doping concentrations in Fig. 7(a) for 1-D GAA, 1-D DG, and 2-D DG FETs. In order to capture only the impact of the different geometries, we consider the same channel material (Si, results obtained with Sentaurus). Regardless of the geometry, G and D increase as the extension doping increases. This behavior can be understood based on the definitions of G and D in (14) and (15), as is known to decrease as doping increases [15], whereas is unaffected by doping [6]. Moreover, as the dimensionality of the device goes from 3-D to 2-D and 1-D, the depletion length increases [15], leading to a decrease in the boundary coupling parameters. Given the qualitatively similar trends of G and D , we further simplify the discussion by only considering G for the remainder of this section (DIBL is shown in Fig. 7(f) for all the cases reported).
Next, we consider how G is influenced by the dielectric environment of low-D FETs. We plot G as a function of spa (with fixed ox ) for different levels of doping in Fig. 7(b) for 1-D GAA CNFET. For higher doping, a high spa increases the depletion in the extensions, reducing G . However, for low doping, where the depletion is already relatively long, the electrostatics is independent of the spacer relative dielectric constant.
The FET width also affects the electrostatics in 1-D DG. Indeed, a wider gate increases the fringe fields terminating in the 1-D extension, leading to an increase in the depletion and resulting in a decrease in G [see Fig. 7(c)].
Next, we consider whether the semiconductor material itself influences the extended SLT coupling parameters. We compare G for 2-D DG FETs with BP and HfS 2 channels because their electron DOS effective masses encompass those of other 2-D materials of interest (e.g., MoS 2 and WS 2 [39]). As shown in Fig. 7(d), the influence of a material's DOS on the coupling (e) and (f) Comparison between SS and DIBL, respectively, for all cases considered in (a)-(d) (circles for Sentaurus, squares for NEGF). To avoid issues due to tunneling with the extraction of SS and DIBL from the transfer characteristics, we used the definitions based on the band profiles in (22) and (23). parameters is negligible for a wide range of doping and relative dielectric constants.
Furthermore, boundary coupling parameters decrease as t ch is reduced, as shown in Figs. 4(c) and (d). The extended SLT can therefore be applied to model the enhanced electrostatic control arising in bulk 3-D-seminconductor materials with few-nm-thin channels. For example, while not considered in this work, extended SLT might be applied to study the tradeoff between electrostatic control and charge density in thin amorphous oxide materials, which are promising candidates for few-nm-thin channels [40], [41].
Finally, Fig. 7(e) and (f) shows the comparison between the model prediction and simulated values for SS and DIBL, respectively, for the cases in Fig. 7(a)-(d). The extended SLT has an average error <0.2% for SS (maximum error < 5%) and <0.5 mV/V for DIBL (maximum error < 6.5 mV/V).

IV. CONCLUSION
We extended the SLT to low-D FETs (e.g., 1-D and 2-D semiconductors) by including the impact of extensions on the channel's electrostatics. The extended SLT, based on three parameters, is fully analytical and accurately reproduces the channel potential and SCEs in low-D FETs. We provided a procedure to extract the new extended SLT parameters from potential profiles or FET transfer characteristics. The understanding gained from the boundary coupling parameters offers new opportunities to engineer low-D FETs. For example, SCEs are reduced by decreasing the extension doping or increasing the spacer dielectric constant. As a result, the extended SLT can be used in combination with DTCO to provide a path toward the introduction of low-D FETs in future technology nodes.

ACKNOWLEDGMENT
Computing resources were provided in part by Compute Canada.