Relaxation Digital-to-Analog Converter with Radix-based Digital Correction

A Relaxation Digital-to-Analog Converter (ReDACs) with a novel, all-digital, radix-based digital correction technique for clock-indifferent linear operation is presented in this paper. The ReDAC architecture proposed in this paper does not require dedicated circuit for frequency tuning, and achieves linearity by digitally pre-processing the DAC input code by a Radix-based Digital Correction (RBDC) algorithm. The effectiveness of the proposed RBDC approach is demonstrated by transistor level simulations on a 10-bit, 1.7MS/s ReDAC in 180nm CMOS. Thanks to the proposed RBDC, under a 16% deviation from the ideal clock period, the maximum INL of the ReDAC is improved from 79.4 to 1.01LSB, its maximum DNL is improved from 158.3 to 0.45LSB and its SNDR is increased from 22.2 (3.4 ENOB) to 58.5dB (9.4 ENOB), at the cost of an increased power consumption from $1.85 \mu \mathrm{W}$ to $9.15 \mu \mathrm{W}$.