Implementation of Self Repair Embedded SRAM Using Selectable Redundancy

In embedding RAM, built in self repair (BISR) is a successful method to improve the yeild. In this work popular march algorithm for memory testing is implemented using a BISR architecture in Modelsim. The BISR architecture is able to eliminate repeat storing of flaws in embedded RAM. Moreover,performance of the BISR for march c- and march ss are compared. This proposed technique is a cost-effective BISR strategy that only stores each defect address once. The presented BISR occupies 20% of the space and can operate at 150MHz.