Design and Evaluation of Large Sized Floating Point Matrix Inversion Modules for Onboard Computer

Modern satellites and aircrafts employ several algorithms to cater for various requirements onboard including control system, image processing, target recognition, image compression, wireless communication and many more. All these algorithms employ matrix algebra including matrix inversion of a large scale floating point matrix. FPGAs are being employed in almost all onboard computers and systems of aircrafts and satellites. This has spearheaded research in the field of hardware implementation and evaluation of large scale floating point matrix inversion methods. In this paper, FPGA implementation of eight floating-point matrix inversion algorithms for an onboard computer is proposed using a novel combination of model based design with high level language programming for FPGA based designs. The proposed designs were evaluated for matrix size of
$120\times 120$
and can be easily scaled to larger matrix sizes.