Optimization of silicon-based on-chip transmission lines in high speed transmitters for broadband interconnection

This paper demonstrates a practical design and analysis of silicon-based on-chip transmission lines (TMLs) for high speed electrical interconnections. The proposed transmitter consists of multiple digitally-controlled amplifiers, high bandwidth (BW) on-chip TMLs, together with input / output buffers leading to the chip input and output pads. The transmitter is implemented in a Bipolar-Complementary Metal Oxide Semiconductor (Bi-CMOS) process, and the on-chip TML features a compact core area of 0.0027 mm
²
. Both simulation and measurement results are analyzed and compared, in order to validate the circuit model and design. Measured with a probe setup, the BW of the on-chip microstrip line achieves 60 GHz, with an insertion loss below 2.3 dB and a return loss better than 10 dB throughout the pass-band, which is compatible for an electrical data path up to 84 Gb/s NRZ.