An Optimization-Based Approach for Analog Circuit Technology Migration

In this paper a new approach for automatic technology migration of analog Integrated Circuits (ICs) is described. The proposed approach uses a software interface between commercial simulators and a Bayesian Optimization (BO) algorithm to automatically size a fixed topology in the target technology node, given a sized schematic in a source technology as golden standard. By using a new acquisition function for BO, we are able to simulate and examine multiple candidate solutions in parallel, thereby reducing the total runtime of the procedure. The proposed approach is demonstrated on two real world circuits, by migrating their schematics from a TSMC 90nm to a TSMC 40nm technology.