LPDDR5 (6.4 Gbps) 1-tap DFE Optimal Weight Determination

SI (Signal Integrity) analysis of a LPDDR5 SoC-DRAM PoP (Package-on-Package) system using 1-tap DFE (Decision Feedback Equalization) is presented. The system was running at 6.4 Gbps with 0.47V VDDQ at SS corner. The DFE mitigates the reflection based ISI and results in improved eye-aperture. DFE has been extensively used in serial differential interfaces such as USBSS and PCIe but their use in LPDDR5 parallel single-ended interface is new and presents unique challenges as the JEDEC standard hexagonal eye-mask defines two timing specifications, namely @Vref+/-0mV and @Vref+/-50mV. Vref being the reference voltage in the eye center used for measuring the eye-opening. Based on the channel analyzed, during Writes, the optimal 1-tap DFE feedback-weight was ~5mV which improved eye-aperture @Vref+/-50mV without degrading the eye-aperture @Vref+/-0mV. Further increasing the feedback-weight resulted in over-equalization causing the eye-aperture @Vref+/-0mV to decrease even though the eye-aperture @Vref+/-50mV kept increasing.