A Low-Noise 320×240 Digital ROIC for SiGe Microbolometers with a Fast Converging Offset Calibration Technique

This paper presents a low-noise 320 × 240 digital readout integrated circuit (ROIC) for SiGe microbolometers with a pitch size of 17 μ m. The ROIC architecture uses a column-shared capacitive transimpedance amplifier (CTIA) that senses the change in resistance of the SiGe microbolometers with respect to the column-shared reference microbolometer pixel. The output voltage of the CTIA is then digitized using a split-successive approximation register (SAR) analog-to-digital converter (ADC). Each 40 columns of the CTIA is connected to a SAR ADC with the help of a 40×1 MUX, which makes 8 parallel-operating ADCs in total. In this way, speed and power requirements of ADCs are relaxed. The offset calibration for the comparator, in the split-SAR ADC is designed using a novel two-step coarse and fine current adjusted technique. The prototype ROIC consumes 118.75 μW power per column while has an NETD of less than 9mK. Simulation results of the proposed offset-calibration technique offers a minimum conversion time of 71.78 ns with a minimum residual voltage of 42 μ V.