Design and Implementation of a Low Power Ternary Content Addressable Memory (TCAM)

Memory has become an essential resource in today's computing systems. The speed of the memory remains a bottleneck in the overall design of various computational systems. Parallel search operations using content addressable memory (CAM) architecture is popularly employed to improve the memory access time. Ternary Content Addressable Memory (TCAM) subsystem includes search operation via content addressing in the designed look up table, to fetch actual data from memory. The TCAM design has shown remarkable performance improvement over years, yet there is a scope to leverage power. A novel power efficient and performance reliable Binary and Ternary CAM memory cells are proposed and implemented, with results presented for 8*8 memory subsystem design.