An Efficient FPGA Implementation of Izhikevich Neuron Model

This paper presents a modified Izhikevich neuron model replacing complex multiplication and division operations with simple binary-based shift operations. A counter-based adder circuit is designed to address the problem that multiple neurons fire spikes simultaneously to one neuron. The proposed model is implemented on FPGA. Results show that the hardware resource utilization of the proposed model is reduced by 87.2% compared with that of the original model and the highest operating frequency is increased from 123.8MHz to 291.8MHz.