3D Wafer-to-Wafer Bonding Thermal Resistance Comparison: Hybrid Cu/dielectric Bonding versus Dielectric via-last Bonding

3D wafer-to-wafer bonding is a promising fabrication method to create 3D systems with a very high interconnect density. The thermal resistance of the 3D bonding interface can represent a significant contribution of the overall thermal resistance in the 3D chip stack and should therefore be accurately characterized. In this paper, we present the experimental characterization of two different types of 3D wafer-to-wafer bonding: Cu/dielectric hybrid bonding and via-last dielectric bonding. First, we introduce the wafer-level test vehicles and the characterization methodology for the analysis of both bonding interfaces. Then, we estimate the thermal resistance of the bonding interface based on a combination of temperature measurements and finite element thermal simulations. Benchmarking of the measurement results with available literature data on thermal resistance values of 3D interfaces shows that wafer-to-wafer bonding results in a reduction of the bonding layer thermal resistance of 5x and 20x for the hybrid bonding and dielectric bonding respectively, compared to the standard die-to-wafer bonding approach with micro-bumps and underfill.