Virtual Process-Based Spacer & Junction Optimization for an Inverter Circuit

An inverter is a basic electronic device used repeatedly in larger circuitry. The performance and overall power handling depend on the design of the
$\pmb{N}$
and PMOS transistors and on the circuit itself. In our study, we model a representative 24 nm fin pitch and 42 nm gate pitch inverter using Coventor SEMulator3D® Virtual Platform. We have investigated an initially deposited spacer thickness process window of 3 nm to 10 nm and a gate width variation from 14 nm to 18 nm. DC performance calculated using drift diffusion, was optimized for junction anneal time, considering a figure of merit using
$\pmb{I}_{on}$
& DIBL for both NMOS & PMOS. AC performance was evaluated with an Elmore delay model, using the drift diffusion-based DC data combined with RC netlist data. Circuit speed gain is obtained with gate length scaling down to 14 nm, but lack of junction abruptness limits the benefit of deposited spacer scaling below 7 nm.