Design of Sequential Circuit Using Data Driven Clock Gating and Multibit Flip-Flop Integration

Flip-flops are one of the most important and basic block of any digital circuits. The power being on the major factor in designing of the digital circuits has to be optimized to improve the performance of the circuit. There are many low power methods available to reduce the power dissipation. the idea here is to combine the low power techniques to order to obtain further power reduction design. The Objectives of the project are to design a high speed, low power D - flip-flop and to design the multibit flip flop and to design data driven clock gating circuit and to combine two different power reduction technique i.e data driven clock gating and multi flip-flop technique and to apply the combined techniques into a sequential design and measure the power utilization and speed of the circuit and contrast it and the conventional design. The LRFF is used to implement the low power techniques. The cadence virtuoso tool is used for the implementation of the circuit and the technology used is 45nm. The results of the power dissipation and is compared with that of the conventional D Flip-flop, the improvement was found to be 36.5% with clock gating of logic structure reduction Flip-flop, and 52.714% with integration of logic structure reduction Flip-flop. Results obtained shows the impact of combining the low power techniques and this basic reduction can reduce the overall power dissipation in the digital circuits.