Steady State Frequency Response Utilizing an Enhanced Chirp Test Signal

One technique to obtain a rapid system frequency response is to excite the system with a chip signal where the frequency of the signal ramps up from a low start frequency to a final high frequency. With such a signal the system is never in steady state. If the ramp were a stair step with multiple periods for each frequency at each stair step, steady state could be achieved but the result will not be rapid. This is especially true where the desired system frequency response starts at a very low frequency where multiple periods of the first frequency could be many tens of seconds. A common technique is to configure the test signal as a Sum of Sines (SOS) where all the frequencies are summed together with the signal duration being a few periods of the lowest frequency. Algorithms to extract the frequency response from such a signal have been developed. A shortcoming of this approach is that this signal has a rogue wave that consumes measurement dynamic range. This limits the signal amplitude that can be allocated to each frequency and becomes a constraint on measurement resolution. With a chirp signal the full dynamic range is available at each frequency. A new variation of chirp along with an advanced algorithm has been developed whereby the rogue wave of the SOS signal is avoided and the signal duration is very close the SOS signal.