Design of 24 GHz High-Linear High-Gain Low-Noise Amplifiers Using Neutralization Techniques

This paper presents two 24 GHz low-noise amplifiers (LNA) using neutralization techniques. By mitigating the intrinsic gate-drain capacitance C
_gd
, the neutralization techniques can reduce the nonlinearity contributions of the output second-order products, and boost gain. According to the closed-form expression of the input third-order intercept point (IIP
₃
), the linearity analysis is presented for design guidelines. The circuits are fabricated in 65 nm bulk CMOS technology. Experimental results show that the two LNAs achieve 23.5 dB and 21.3 dB gain, 3.4 dB and 3.7 dB noise figure, 16.5 dBm and 17 dBm output third-order intercept point (OIP
₃
), 12 mW and 18.5 mW power consumption, respectively.