Design and Simulation of 16×16 bit Iterative Logarithmic Multiplier for Accurate Results

Multiplication is a basic arithmetic operation. Multiplication operations such as Fast Fourier Transforms, Multiplication and accumulation units, Convolution are some of the computation-intensive arithmetic functions often encountered in Digital Signal Processing applications. Usually, Logarithm based multipliers are used in these cases which introduce certain errors. These errors are approximated by various methods. In this paper a simple architecture of a 16×16 logarithm based multiplier is proposed which uses simple combinational and sequential circuits to obtain an exact product. The multiplier has an arbitrary execution time with the maximum execution time being 15 clock cycles and mean being 7.5 clock cycles. This architecture is designed and simulated in `ModeISim' simulation tool.