Fast, Secure and Efficient Vedic Approach for Cryptographic implementations on FPGA

Cryptography is the best way to provide security and Cryptographic implementations on FPGA provides hardware security advantage along with it. ECC (Elliptic Curve Cryptography) provides the best security among all other standards. The only disadvantage of it was performance because of it's a type of Asymmetric Cryptography. In some literature we study about trade-off between security and performance in terms of speed and complexity of the system. In this Paper we provide efficient approach for Cryptography where Security is improved with improvement in performance by replacing the conventional multiplier (16 bit) by Vedic multiplier (32 bit). The proposed multiplier recursively processes data as 32-bit double words. This multiplier when employed in ECC algorithm reduces drastically the total area utilization. The complete proposed design is synthesized and simulated using Xilinx 14.5 software. Experimental findings show a remarkable improvement in area efficiency, time complexity, and power requirements when comparing with other such implementations.