Chip-to-Wafer (C2W) flip chip bonding for 2.5D high density interconnection on TSV free interposer

The requirements of electronic packages with higher input/output (I/O) density at smaller bump pitches have driven the demand of 3D packaging technologies [1]. The TSV technology is considered as the more advanced technique for high performance IC packaging solution. It uses vertical interconnection which forms metallic vias through stacked dies [2]. It also allows multi-chip stacking, enhancing the 3D chip integration capability. The requirements of high density interconnection and improved electrical performance have resulted in more packaging applications using Si interposers with TSV vias [3]. However the fabrication process of TSV vias is expensive and involves a lot of process steps. It also poses different process challenges and requires many wafer inspection process such as the inspection of the sidewall of the TSV via, the bottom of the TSV via and the uniformity on the TSV via diameter [4]. Xray inspection is also required to inspect the Cu-filled TSV via and to check for any voids in the TSV via. In this work, we highlighted the challenges and difficulties of chip to wafer bonding and underfill dispensing process for test dies with high I/Os onto a TSV free interposer (TFI). Detailed study and process development is required to resolve the assembly process challenges. One larger chip 15×15mm known as the Graphics Processing Unit (GPU) and 2 smaller chips 5.5mm×7mm known as the High Bandwidth Memory (HBM) were attached onto the TFI interposer (25mm × 18mm) [5]. We selected 3 types of underfill with a no-clean flux for the chip to wafer flip chip and underfill process. The flip chip process involves the using no-clean flux and subjected to a conventional conveyor reflow oven with temperature set at 260°C. Capillary underfill dispensing process is then applied onto the assembled C2W 8 inch wafer to encapsulate the C4 bumps and microbumps. A simple underfill dispensing DOE is evaluated to solve the underfill voids issue observed on the highly dense interconnects. Finally, overmolding is done on the assembled package.