A novel annular ring design for improved plated-thru-hole impedance matching

A novel and patent-pending [1] routing configuration to address the multi-reflection noise caused by the vertical interconnect viz. plated-through-hole (PTH) is presented in this paper. The PTHs are frequently found in any packaging and printed circuit board (PCB) designs for signaling transition from one lateral layer to another. The reflection noise caused by impedance mismatch ascribed to the over-capacitive nature of PTH structure is notoriously associated to degrade and reduce high-speed link margin. The proposed inventive solution is particularly significant to enable multi-Gbps differential high-speed input/output (HSIO) links, such as USB 3.1 Gen2 and Thunderbolt 3 with frequencies running beyond 10Gbps. Though the modeling and simulation analysis conducted and presented in this paper focused on package PTH, the invention is applicable to package ball-grid-array (BGA) pad as well as printed circuit board (PCB) PTH, since each structure produces the same electrical impairment fundamentally. 3-dimensional electromagnetic field modeling and analytical data have shown encouraging data, with up to 20% eye margin improvements thus illustrating the feasibility of this inventive design. This routing scheme is a viable candidate for high-speed interconnect design to enhance highperformance systems.