Challenge and warpage optimization of thermal compression bonding technology on coreless substrates

Recently, Flip Chip Packages provide the ideal solution for low to high I/O, high electrical performance demand in handheld devices where high frequency, high speed are required. To approach these requirements, we present an alternative fine bump pitch solution of low cost and high throughput which used thermal compression bonding (TCB) combining with molding underfill (MUF) technology and comparing with traditional mass reflow (MR). As we known MR is the lowest cost and mature process in general. By using coreless substrate with embedded fine-trace substrate (ETS) technology to achieve package miniaturization requirement. Comparing with conventional substrate, coreless substrate technology eliminates the substrate core, and utilize build-up layers to interconnect the chip and the PCB board. It brings about not only low Z-height, lightweight, but also short interconnection distance and good power integrity. The ETS coreless technology is a promising solution for the next generation substrate. A Flip Chip Scale Package (FCCSP) and ETS coreless substrate combination are used to this paper experiment. The major challenge is thinner ETS coreless substrate to induce warpage concern which because of no core material as supporting material, also ETS coreless substrate no rigid product characteristic and easy to bring handling issue during manufacturing and assembly process. Thermal compression bonding could offer less thermal budget and stress to mitigate CTE mismatch between silicon chip and coreless substrate. The study result of warpage control between TCB and mass reflow process, the TCB could be provided less warpage behavior after compared to traditional mass reflow, also this TCB technology is popular used for thin core, coreless and advance silicon node product field. The characterization analysis will utilize simulation methodology & typical reliability testing (Temperature Cycle Test, un-bias HAST and High Temperature Storage Test) results as a verification monitor items for TCB process with ETS coreless structure feasibility evaluation. Finally, this paper will find out the suitable key process index for future product application.