Integration benefits and challenges on Fan-Out to enable system in package for IoT/Wearable Devices

Because of the rapid spread of portable electronic products and Internet of Things (IoT) / Wearable devices along with the increase in the use of video streaming, photo sharing, and also other data-intensive applications in recent years have driven the development of IC packaging towards on smaller package size, better electrical and thermal performance, higher I/O count, as well as 3D stacking for heterogeneous integration [1]. Therefore, the advanced packaging technology also has been migrated from a lead frame base, substrate base to a wafer-level package which is an emphasis on the next semiconductor's application. For wafer-level package, different from conventional Fan-In Wafer Level Package (FI-WLP) with limited I/O count and incompact pitch to printed circuit board (PCB) count in next level interconnection, Fan-Out Wafer Level Package (FO-WLP) is introduced to allow for higher ball count wafer-level package, by extending the package size through the redistribution layer (RDL) on an encapsulation beyond the area of the chip. The Fan-Out innovation from single chip design as the key bridging technology for more advantageous extensions into a functional integration process of Fan-Out System-in-Package (FO-SiP) : multiple chips with difference wafer node and function feature, memory die as well as application processors in an approach on package size reduction to increase battery size for usage extending, high performance and systemization implemented. In this paper, the characterization study and development with typical package level reliability testing (Temperature Cycle Test, High Temperature Storage Life Test, Unbiased High Accelerated Stress Test) are built to demonstrate integration benefits and challenges on Fan-Out technology to enable system in package for IoT / Wearable devices with the rapidly moving trend towards to FO-SiP solution.