Probablity and simulation based design of fixed width multiplier

This paper proposes an error compensation circuit for fixed-width multiplier based on probability and computer simulation (PACS), whereas the solution provides highest accuracy, low power consumption with high speed. Being highly accurate, the proposed PACS approach is area-effective as compared to Multilevel conditional Probability (MLCP) method. The proposed 8×8 bit fixed width multiplier is designed using Xilinx. Significant reduction in FPGA resources, delay and power can be achieved using fixed width multiplier with PACS instead of MLCP method.