Limitations of interference analyses on multicore processors

This paper presents a status on a continuing research thrust on assurance methods for multicore processors used in avionics equipment. Today's multicore processors introduce new challenges, forcing assurance methods to adapt to their intrinsic complexity, especially parallelism in software execution. Tackling interference issues within assurance methods is still an open problem today, with no consensual approach or official guideline. In the previous installment of the research on MCP assurance methods, the authors developed the notion of interference analysis and detailed the related challenges. This paper focuses on the limits of these interference analyses, i.e. the conditions under which defining and/or implementing a given method would raise major issues, leading to an unsustainable complexity for the equipment development. The objective is not to point out a specific method to use, but rather to highlight foreseeable good and bad properties of interference analysis methods, and how to reach a good compromise between good and bad. These properties are summarized as a set of viewpoints, which are further illustrated on an example.