29.2 A transmitter and receiver for 100Gb/s coherent networks with integrated 4×64GS/s 8b ADCs and DACs in 20nm CMOS

At rates of 100Gb/s and above, CMOS DSP-based transceivers integrated with high-sampling-rate data converters are critical to realize the phase-sensitive modulation schemes based on coherent detection that are essential to metro and long-haul networks [1]. To support dual-polarization QPSK format, quad low-power DACs and ADCs are needed and precise phase alignment has to be maintained between XI, XQ, YI, and YQ channels, in order to transmit and extract the phase information in the coherent system, as shown in Fig. 29.2.1. For long-haul transmission at 100Gb/s, because of the FEC overhead, the baud rate per channel can be as high as 32Gb/s. In addition, the receiver often requires double sampling at 64GS/s for robust clock-data recovery and SNR improvement for stressed channels. Double sampling also enables the DSP to implement more complicated equalization schemes and more flexible spectrum engineering at high frequency on the transmitter side. This paper reports the receiver and transmitter fully integrated in a 100G coherent DSP chip, using 4×64GS/s ADCs and DACs with 8b resolution, fabricated in a standard 20nm CMOS process.