A Passive Equalizer Design for Shielded Differential Through-Silicon Vias in 3-D IC

This letter develops a simplified circuit model for the shielded differential through-silicon vias (SD-TSVs). The model is consisted of four frequency-independent elements and can accurately predict the insertion loss of the SD-TSVs up to 20 GHz. Based on the model, a parallel resistor-capacitor equalizer is proposed. The proposed passive equalizer achieves wide-band equalization and perfect compensation for high-speed differential signaling.