A pipeline architecture for traffic sign classification on an FPGA

This paper presents an efficient FPGA design that can classify 48 different traffic signs at real-time. The method is based on histogram of oriented gradients (HOG) feature extraction and support vector machine (SVM) for classification. A full-pipeline, resource efficient architecture is presented with detail design of each block. The FPGA implementation has a system clock of 241.7 MHz with an absolute response time of 6.5 s. Taking streaming pixel input, the system throughput is about 106 times faster than the same algorithm executed on a general purpose processor.