A process corner detection methodology for resilience towards process variations using adaptive body bias

The nanometre scale technology is fundamentally different from its predecessors as they are exposed to a wide variety of new effects that are induced on the transistor chips. One of the reliability degradation effects is process variation which plays a relevant mantle as it leads to performance degradation. The work presented in this paper explains an all process corner (SS, SF, FS & FF) detection scheme for providing tolerance towards process variations using Adaptive Body Bias (ABB). In this scheme, an on-chip monitor detects the process corner at which the circuit is operating and a corresponding adaptive body bias is generated by the body biasing circuit which is supplied to the transistors. The simulations are performed taking V
_BB
as 0, i.e., No Body Bias (NBB) and by supplying a finite adaptive body bias (ABB) voltage to the transistors on the chip and their corresponding mean and variance have been calculated using Monte Carlo histograms. Simulations have been performed on a critical path which has been extracted from a microprocessor at 32 nm predictive technology model using HSPICE. Monte Carlo simulations of 10,000 runs demonstrate that the proposed approach provides tolerance to process variations under all process corners. The proposed approach has shown to reduce the impact of process variations on frequency, dynamic power & leakage power and a reduction in the values of relative standard deviation (σ/μ) conforms to our circuit approach.