Research of silicon cap for epitaxy sige in source/drain regions

SiGe epilayer is extensively used as stressor in source/drain regions in PMOS. However, it is a big challenge to form germanosilicide with low contact resistivity due to poor thermal stability at high temperature. Therefore, silicon cap deposited on SiGe is applied to reduce contact resistance. In static random access memory (SRAM) area, silicon cap profile is apt to be un-conformal due to SiGe pattern effect. In this paper, the effect of silicon source, etching gas, doping gas and temperature on Si cap profile was investigated. Finally conformal silicon cap was obtained on SiGe epilayer with relatively high growth rate, which could reduce contact resistance.