Towards formal validation: Symbolic simulation of SystemC models

With increasing complexity of systems, specifications are becoming more and more comprehensive and often inconsistent or incomplete. To validate a system regarding realistic use cases, systems are simulated “in the loop”, including the application and usage scenarios. This paper describes a first approach to analyze software systems “in the loop” in a more comprehensive way by symbolic simulation. For this purpose we propose a new approach to separate modeling- and implementation languages from formal methods. For demonstration, we implemented it in the SYCYPHOS framework based on C++ and SystemC AMS.