Stacked-etch induced charge loss in Hybrid Floating Gate cells using high-κ Inter-Gate Dielectric

We investigate the stacked-etch induced charge loss of multi-layer (HfAlO-Al
2
O
3
-HfAlO) Inter-Gate Dielectric (IGD) together with a thin Hybrid Floating Gate (HFG), in aggressively scaled planar NAND cells. The results obtained using Bias-Post Program Discharge on no-overlap/overlap capacitors and cells, clearly point out charge loss due to etching damage in Tunnel Oxide (TuOx). On the other hand the inter-gate dielectric damage by stacked etch can be avoided. The etch damage is high with TiN control gate and moderate with amorphous-Si control gate. For short cell featuring Poly-Si control gate, the charge loss occurs through inter-gate dielectric due to the poor interface between inter-gate dielectric / control gate and a degraded intergate dielectric, as suggested by Gate-Side Trap Spectroscopy by Charge Injection and Sensing (GS-TSCIS) and TEM.