An asynchronous bus bridge for partitioned multi-soc architectures on FPGAs

Recent FPGA families exhibit a bandwidth gap that is inverse to the widely known memory bottleneck of hardwired platforms: Behaviorally described soft processors are comparatively slow whereas FPGAs offer high-throughput state-of-the-art memory attachments. We show that it is possible to take advantage of this bandwidth gap to host functionally partitioned safety- and security-critical software functions. Our proposed multisystem architecture instantiates multiple self-contained local systems on a reconfigurable platform that operates from a shared but partitioned memory. We benchmark and evaluate a novel asynchronous bus bridge and demonstrate that the asynchronous architecture is scalable both at run-time and during place-and-route.