Numerical comparison of the thermal performance of 3D stacking and Si interposer based packaging concepts

In this paper, the thermal performance and the thermal die-to-die coupling are compared for the case of a 3D stacked configuration and a Si TSV-interposer by means of detailed thermal finite element simulations. The comparison is applied to packages with two components: 10×10mm
²
logic chip and a 2×10mm
²
temperature sensitive SerDes chip. A one-to-one comparison is made for package configurations without heat sink and for packages with integrated heat spreader and high performance heat sink.