FPGA implementation of retimed low power and high throughput DCT core using NEDA

Discrete Cosine Transform (DCT) is a popular technique used for converting signal into elementary frequency components. NEw Distributed Arithmetic (NEDA) is an efficient method for implementing inner products without using multipliers and ROM. In this present design, we have proposed the implementation of 1D DCT using NEDA, considering retiming technique. The outputs are obtained at every clock cycle. The maximum frequency obtained is 311.943 MHz and the throughput is of 3431.384 Mbit/s. The slice delay product of the proposed design is 1.734. The proposed design consumes 2.76 W at its maximum frequency.