Understanding the effect of PCB layout on circuit performance in a high frequency gallium nitride based point of load converter

The introduction of enhancement mode gallium nitride based power devices such as the eGaN
^®
FET offers the potential to achieve higher efficiencies and higher switching frequencies than possible with Silicon MOSFETs. With the improvements in switching performance and low parasitic packaging provided by eGaN FETs, the PCB layout becomes critical to converter performance. This paper will study the effect of PCB layout parasitic inductance on efficiency and peak device voltage stress for an eGaN FET based point of load (POL) converter operating at a switching frequency of 1 MHz, an input voltage range of 12-28 V, an output voltage of 1.2 V, and an output current up to 20 A. This work will also compare the parasitic inductances of conventional PCB layouts and propose an improved PCB design providing a 40% decrease in parasitic inductance over the best conventional PCB design.