40-44 GHz MMIC Frequency Tunable Butler Matrix

Electronically scanned phased arrays with simplified, passive beamforming networks can reduce biasing and control circuitry complexity, thus reducing size, weight, power, cost, and cooling (SWaPC2) trade-offs and improving linearity. On the other hand, circuit miniaturization is desired to facilitate scalability in frequency and number of elements. Nonetheless, applications like low small satellites for LEO constellations need improved new topologies of beamforming networks to be applied in millimeter-wave phased arrays that provide tunability, such as mismatch recovery or progressive phase shift correction over frequency. This work presents the design of a frequency-tunable, switched beamforming network operating in the 40–44 GHz bandwidth (Fig. 1). The circuit topology consists of a 4×4 Butler matrix modified by introducing tunable phase shifters at the outer arms and including attenuators in the inner arms to keep amplitude balance over ports and frequency. The circuit is integrated on a WIN Semiconductors 2-mil InGaAs PP10-20 semiconductor process. The Butler matrix core design uses 8.7 dB tandem couplers to achieve 3 dB power division; a ground plane shorted by vias is placed between individual couplers to achieve 90 degrees of phase shift between ports. Cross-overs are designed in CPW to increase isolation between RF paths. The reflective-type phase shifters topology is based on the same couplers used in the Butler matrix and cold FETs operating as varactors, with a cascaded short-circuit stub to increase and equalize phase-shift range over frequency. Fixed Schiffmann phase shifters are introduced to compensate for second cross-over and internal arms line delays. Bondwire-compensated loads are incorporated into the chip for easy on-wafer characterization using a 2-port vector network analyzer and post-processing the measured 2×2 matrices to obtain the full 4×4 S-matrix characterization. The analysis is performed by co-simulation between Cadence AWR full-wave and circuit simulator, using the foundry PDK models. Figure 2 (top) shows the matching levels and insertion loss at ports P2, P3, P4, and P5 when port PI_State1 is excited with a CW signal and PI_State2,3,4 are connected with 50-ohms and over frequency. The columns show three states of phase-shifters tunability for VCtrl={-I.2, -0.706, -0.2}V. Figure 2 (bottom) shows the progressive phase shift between ports P2-P3 (red), P3-P4 (blue), and P4-P5 (gray). It can be observed that curves cross at 44 GHz (left), 42 GHz (center), and 40 GHz (right), showing progressive phase shift balance over ports.