Design and Implementation of Optimized Resource Low-Power SoC Multi-Soft-Processor FPGA Hardware Acceleration Architecture for Fast Digital Image Processing

This paper focuses on designing, implementing, and optimizing a distributed multi-soft-processor SoC low-power FPGA-based software-hardware co-design architecture for fast digital image processing computing acceleration. The paper demonstrates an on and off-the-chip augmented hardware architecture implementation to overcome Memory, Cost, Size, and Power prohibitive resource constraints. This implementation experimentally achieves an optimized accelerated digital image processing and digital filtering execution time. The method achieves 80 times computational speedup with the proposed augmented hardware-accelerated optimization scheme compared to an initial practical implementation without hardware acceleration. This design is implemented on an SoC Altera Cyclone- V FPGA. In this design, an FPGA Multi Softcore Processor is instantiated in the fabric and interfaced with an external SDRAM via a 16-bit Memory Controller Intellectual Property (IP) core. An 8-bit intensity resolution image (up to 1280 x 1280 pixels, but not limited) was imported from a PC (via Serial Communication) to the FPGA for Sobel spatial filter processing. Each Soft Core was memory mapped to each image segment to create a parallel multiprocessing architecture. Multiple Sobel Filters are written and synthesized in the fabric. The Register Transfer Logic (RTL) code is written in VHDL and Verilog as a Hardware Description Language (HDL) to accelerate the design implementation. A different number of Softcore Processors in conjuncture with accelerated hardware are tested to compare the resulting computational efficiency. The timings between accessing the on-chip SRAM and the off-chip SDRAM can also be compared. In the final analysis, understanding that the FPGA Softcore using C is quick to implement and flexible to interface with, but it is a non-deterministic and sequentially executed process, and that the FPGA Fabric using HDL is rigid and constraint-driven, but no overhead, implemented in fabric, deterministic, concurrently executed parallel processes. This paper shows a more resource-efficient design that can compete against much larger, more expensive, faster memory and power-hungry designs.