An FPGA Implementation of Turbo Decoding in VDES

VDES (Very High Frequency Data Exchange System), as an enhancement and upgrading of AIS, further enhances the development of maritime communications and has a wide range of application prospects. The ASM and VDE integrated in VDES use Turbo code to enhance the receiver's error correction capability, while the Turbo code corresponds to different Link IDs of ASM or VDE with multiple coding rates, and different Link IDs in the frame structure also make some data in the coding process differences, these problems bring challenges to the realization of Turbo decoding in VDES. Based on this, this paper proposes a Turbo decoding implementation method for the nature of Turbo codes in VDES system, and verifies the feasibility of the method in FPGA. In this paper, the theory of Turbo decoding is introduced in detail, the applicability of Turbo decoding based on Max-Log-MAP component decoder in VDES is determined through simulation, and the adaptation of Turbo decoding scheme to different Link IDs is realized in FPGA logic design, and the validation results and test data prove that the Turbo decoding scheme has the ability to adapt to different Link IDs in VDES.