Asymmetrical Eleven-Level Multilevel Inverter with Low Switching Count and Voltage Stress

This research presents an eleven-level multilevel inverter with decreased switching count and voltage stress. There are only 7 switches in the architecture, including 1 bidirectional switch and 2 capacitors. The inverter circuit is given a gate pulse using a straightforward nearest level control (NLC), which is a fundamental switching frequency-based approach. To demonstrate the advantages of the presented topology, a comparison with recent topologies in terms of switches, diodes, sources, and capacitors employed in numbers is made. According to the IEEE 519–2014 standard, the total harmonic distortion (THD) is 8.6%, which is almost within acceptable bounds. Eventually, using the software PLECS and MATLAB (SIMULINK), the recommended architecture has been operationally and functionally simulated. Its experimental validation is also being done on the setup for various loading circumstances.