A new method of power analysis of Network-on-Chip using analytical modelling

The complexity of communication in multi-core, many-core processors and Multiprocessor System-on-Chip (MP- SoC) has increased significantly resulting in the adaptation of on-chip interconnection network (Network-on-Chip). The performance of NoC impacts the performance of the processor directly. Throughput and latency, power consumption are the metrics that indicate the performance of an NoC. In this article we propose a methodology that combines simulation and analytical results for power analysis of an NoC. Queuing theory based analytical model is used. We carried out power analysis of NoC under different scenarios involving calculation of transition probability using Vivado XSIM simulator and probability equations. We have obtained the key parameters of emerging 10 nm and 7 nm technologies from BSIM-CMG, PTM, IRDS reports and used them for the power analysis of NoC router components for 10nm and 7nm technologies. Finally we present the results of latency, throughput and power measurements of NoC for real traffic (PARSEC benchmark traffic).