Low Power Flip-Flop Design with Reduced Leakage using Sleepy Stack and Stack Power Gating Technique

Leakage power consumption in current CMOS technology remains challenging which in turn contributes to the overall power dissipation. A flip-flop design using sleepy stack inverter pair along with stack power gating technique is proposed inthis paper to attain higher power efficiency with reduced leakage. Unlike conventional flip-flop design, sleepy stack inverter techniqueretains the logic in sleep state and power gating techniques involved results in efficient power consumption. Although the proposed technique provokes area overhead, lowest power consumption along with reduced leakage is acquired. As the proposed flip-flop design incorporates low power and efficient leakage profile, power performance of the sleepy stack inverter with stack power gating has been improved to 50.25% and leakage power has efficient improvisation of 41%.