An LUT-based error diagnosis technique improved in multiplicity of rectifiable errors

In an LSI design process, engineering change orders (ECO's) are often given due to logic design errors, changes of specification, and timing issue. This paper presents an improved technique called EXL/sub IT/ to rectify multiple logic design errors using LUT-based circuit model, which is needed to rectify errors with compound cells often used in standard-cell design. In contrast to the conventional technique: EXL/sub TV/ applicable only to four errors at the maximum, EXL/sub IT/ rectifies ten errors by employing iterative diagnosis procedure for subcircuits extracted based on the correctness of primary output functions. By handling the subcircuits, EXL/sub IT/ reduces both the number of LUT's and the number of errors to be considered at once. Experimental results demonstrate that most of circuits including eight to ten design errors can be rectified within shorter processing time.