New guideline of Vdd and Vth scaling for 65nm technology and beyond

We show new guideline of Vdd and Vth scaling for logic blocks and high density SRAM cell from low power dissipation viewpoint. New degradation mode for inverter delay becomes major obstacle for Vdd scaling in the future. Low Vdd and low Vth should be applied only for circuits with high switching activity. In other portions, Vdd should be kept around 1-1.2V. High density SRAM with beta ratio of 1(0.56 /spl mu/m/sup 2/) operates at 0.7V by choosing optimum Vth.