VLSI design of a reconfigurable multi-mode Reed-Solomon codec for high-speed communication systems

This paper presents the VLSI design of a reconfigurable multimode Reed Solomon (RS) codec for various high-speed communication systems. Our decoder design is based on the Euclidean algorithm such that the datapath units are regular and simple. With its ability to support a variety of (n, k, t) RS specifications (0/spl les/t/spl les/8) and (0/spl les/n/spl les/255), this RS codec design is suitable for multi-mode systems such as the xDSL and the cable modem systems. The chip operates at a clock frequency of 100 MHz and has a data processing rate of 800 Mbits/s in 0.35 /spl mu/m CMOS technology at the supply voltage of 3.3 V. The total gate count is 34,647 gates and the core size is only 1,578 /spl times/ 1,560 /spl mu/m/sup 2/.