Small scale integrated technology for HTS RSFQ circuits

A technology for fabrication of YBCO ramp junctions on a superconducting ground plane is developed and evaluated. The technology is based on a two-layer, S-I, structure or on a four-layer, S-I-S-I, structure grown in situ with YBCO superconductor and with multilayer insulator of PBCO/STO/PBCO. Ramps for junctions, via connections and crossovers are formed by Ar ion milling under rotation and the ramp angle is less than 30/spl deg/ for all directions. A 20-25 nm thick Ga-doped PBCO was used as a barrier for Josephson junctions. One additional YBCO layer, for junction top electrodes and wiring, is deposited and patterned. Surface roughness of multilayers is characterized by AFM and is related to the junction parameters. Transport properties of junctions, via connections and crossovers are evaluated.