A low power MMSE receiver architecture for multi-carrier CDMA

The power consumption of a minimum mean square error (MMSE) multi-carrier CDMA (code division multiple access) receiver implemented in digital hardware is considered. A new low power block based architecture is implemented for the combiner subsystem, and compared with a multiply accumulate circuit approach. Simulations using data consistent with typical performance of a multi-carrier CDMA receiver indicate that the block based approach can produce a power reduction of around 50%.