A four-channel self-calibrating high-resolution time to digital converter

A four channel, self-calibrating, High Resolution Time to Digital Converter (HRTDC) with an RMS error of 35 ps over a dynamic range of 3.2 /spl mu/s has been developed. Its architecture is based on an array of delay locked loops and an 8-bit coarse time counter driven by an 80 MHz reference clock. Time measurements are buffered in two time registers per channel followed by a common 32 words deep read-out FIFO. The HRTDC has been built in a 0.7 /spl mu/m CMOS process using 23 mm/sup 2/ of silicon area.